AM1707_1008 Datasheet, PDF (95/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
www.ti.com
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
6.17 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
• Flexible clock and frame sync generation logic and on-chip dividers
• Up to sixteen transmit or receive data pins and serializers
• Large number of serial data format options, including:
– TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
– Time slots of 8,12,16, 20, 24, 28, and 32 bits
– First bit delay 0, 1, or 2 clocks
– MSB or LSB first bit order
– Left- or right-aligned data words within time slots
• DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers
• Extensive error checking and mute generation logic
• All unused pins GPIO-capable
• Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample
rate by making it more tolerant to DMA latency.
• Dynamic Adjustment of Clock Dividers
– Clock Divider Value may be changed without resetting the McASP
The three McASPs on the device are configured with the following options:
Table 6-43. McASP Configurations⁽¹⁾
Module
McASP0
McASP1
McASP2
Serializers AFIFO DIT
16
64 Word RX
64 Word TX
N
12
64 Word RX
64 Word TX
N
4
16 Word RX
16 Word TX
Y
Pins
AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0, AFSX0, AMUTE0
AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1, ACLKX1, AFSX1,
AMUTE1
AXR2[3:0], AHCLKR2, ACLKR2, AFSR2, AHCLKX2, ACLKX2, AFSX2, AMUTE2
(1) Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.
Peripheral
Configuration
Bus
McASP
DMA Bus
(Dedicated)
GIO
Control
DIT RAM
384 C
384 U
Optional
Transmit
Formatter
Receive Logic
Clock/Frame Generator
State Machine
Clock Check and
Error Detection
Transmit Logic
Clock/Frame Generator
State Machine
Serializer 0
Serializer 1
Pins
Function
AHCLKRx Receive Master Clock
ACLKRx Receive Bit Clock
AFSRx
Receive Left/Right Clock or Frame Sync
AMUTEINx
AMUTEx
The McASPs DO NOT have
dedicated AMUTEINx pins.
AFSXx
Transmit Left/Right Clock or Frame Sync
ACLKXx Transmit Bit Clock
AHCLKXx Transmit Master Clock
AXRx[0] Transmit/Receive Serial Data Pin
AXRx[1] Transmit/Receive Serial Data Pin
Receive
Formatter
Serializer y
McASPx (x = 0, 1, 2)
AXRx[y] Transmit/Receive Serial Data Pin
Figure 6-33. McASP Block Diagram
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
95
Submit Documentation Feedback
Product Folder Link(s): AM1707