AM1707_1008 Datasheet, PDF (53/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
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System Interrupt
0
1
2
3
4
5
6
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12
13
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16
17
18
19
20
21
22
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49
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
Table 6-7. AINTC System Interrupt Assignments
Interrupt Name
COMMTX
COMMRX
NINT
PRU_EVTOUT0
PRU_EVTOUT1
PRU_EVTOUT2
PRU_EVTOUT3
PRU_EVTOUT4
PRU_EVTOUT5
PRU_EVTOUT6
PRU_EVTOUT7
EDMA3_CC0_CCINT
EDMA3_CC0_CCERRINT
EDMA3_TC0_TCERRINT
EMIFA_INT
IIC0_INT
MMCSD_INT0
MMCSD_INT1
PSC0_ALLINT
RTC_IRQS[1:0]
SPI0_INT
T64P0_TINT12
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
-
PROTERR
-
EDMA3_TC1_TCERRINT
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
EMIF_MEMERR
GPIO_B0INT
GPIO_B1INT
GPIO_B2INT
GPIO_B3INT
GPIO_B4INT
GPIO_B5INT
GPIO_B6INT
GPIO_B7INT
Source
ARM
ARM
ARM
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
EDMA CC Region 0
EDMA CC
EDMA TC0
EMIFA
I2C0
MMCSD
MMCSD
PSC0
RTC
SPI0
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
Reserved
SYSCFG Protection Shared Interrupt
Reserved
EDMA TC1
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
EMIFB
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
GPIO Bank 6 Interrupt
GPIO Bank 7 Interrupt
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Peripheral Information and Electrical Specifications
53
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