AM1707_1008 Datasheet, PDF (69/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
6.11.6 EMIFA Electrical Data/Timing
The following assume testing over recommended operating conditions.
No.
19 t_su(DV-CLKH)
20 t_h(CLKH-DIV)
Table 6-20. EMIFA SDRAM Interface Timing Requirements
PARAMETER
MIN
Input setup time, read data valid on EMA_D[15:0] before EMA_CLK
rising
1.3
Input hold time, read data valid on EMA_D[15:0] after EMA_CLK
rising
1.5
MAX
UNIT
ns
ns
No.
1
2
3
4
5
6
7
t_c(CLK)
t_w(CLK)
t_d(CLKH-CSV)
t_{oh(CLKH-CSIV)}
t_d(CLKH-DQMV)
t_{oh(CLKH-DQMIV)}
t_d(CLKH-AV)
8
t_oh(CLKH-AIV)
9
t_d(CLKH-DV)
10 t_oh(CLKH-DIV)
11 t_d(CLKH-RASV)
12 t_{oh(CLKH-RASIV)}
13 t_d(CLKH-CASV)
14 t_{oh(CLKH-CASIV)}
15 t_d(CLKH-WEV)
16 t_{oh(CLKH-WEIV)}
17 t_{dis(CLKH-DHZ)}
18 t_{ena(CLKH-DLZ)}
Table 6-21. EMIFA SDRAM Interface Switching Characteristics
PARAMETER
MIN
Cycle time, EMIF clock EMA_CLK
10
Pulse width, EMIF clock EMA_CLK high or low
3
Delay time, EMA_CLK rising to EMA_CS[0] valid
Output hold time, EMA_CLK rising to EMA_CS[0] invalid
1
Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid
Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid
1
Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0]
valid
Output hold time, EMA_CLK rising to EMA_A[12:0] and
EMA_BA[1:0] invalid
1
Delay time, EMA_CLK rising to EMA_D[15:0] valid
Output hold time, EMA_CLK rising to EMA_D[15:0] invalid
1
Delay time, EMA_CLK rising to EMA_RAS valid
Output hold time, EMA_CLK rising to EMA_RAS invalid
1
Delay time, EMA_CLK rising to EMA_CAS valid
Output hold time, EMA_CLK rising to EMA_CAS invalid
1
Delay time, EMA_CLK rising to EMA_WE valid
Output hold time, EMA_CLK rising to EMA_WE invalid
1
Delay time, EMA_CLK rising to EMA_D[15:0] 3-stated
Output hold time, EMA_CLK rising to EMA_D[15:0] driving
1
Table 6-22. EMIFA Asynchronous Memory Timing Requirements⁽¹⁾
No. PARAMETER
E t_c(CLK)
2 t_{w(EM_WAIT)}
12 t_{su(EMDV-EMOEH)}
13 t_{h(EMOEH-EMDIV)}
14 t_{su (EMOEL-EMWAIT)}
READS and WRITES
Cycle time, EMIFA module clock
Pulse duration, EM_WAIT assertion and
deassertion
READS
Setup time, EM_D[15:0] valid before EM_OE
high
Hold time, EM_D[15:0] valid after EM_OE high
Setup Time, EM_WAIT asserted before end of
Strobe Phase⁽²⁾
WRITES
MIN
10
2E
3
0
4E+3
NOM
MAX
7
7
7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
ns
7
ns
ns
7
ns
ns
7
ns
ns
7
ns
ns
MAX UNIT
ns
ns
ns
ns
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-18 and Figure 6-19 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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