AM1707_1008 Datasheet, PDF (50/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
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Table 6-5. Allowed PLL Operating Conditions
No.
PARAMETER
1
PLLRST: Assertion time during
initialization
Default
Value
N/A
MIN
1000
MAX
N/A
UNIT
ns
Lock time: The time that the application
2
has to wait for the PLL to acquire locks
before setting PLLEN, after changing
N/A
N/A
PREDIV, PLLM, or OSCIN
3
PREDIV
4
PLL input frequency
( PLLREF)
5
PLL multiplier values (PLLM) ⁽¹⁾
6
PLL output frequency. ( PLLOUT )
7
POSTDIV
/1
/1
12
x20
x4
N/A
400
/1
/2 ⁽²⁾
Max PLL Lock Time = ^{2000 N}
m
where N = Pre-Divider Ratio
M = PLL Multiplier
/32
50
x32
600 ⁽²⁾
/32
OSCIN
cycles
(1)
ns
MHz
MHz
ns
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 400 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed 300 MHz. The Post Divider and SYSCLK divider values must be
chosen such that the CPU clocks do not exceed 300 MHz.
(2) PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL
output clock.
50
Peripheral Information and Electrical Specifications
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