AM1707_1008 Datasheet, PDF (1/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
www.ti.com
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
AM1707 ARM Microprocessor
Check for Samples: AM1707
1 AM1707 ARM Microprocessor
1.1 Features
123
• Highlights
– 375/456-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Programmable Real-Time Unit Subsystem
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
– Two Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– Three Multichannel Audio Serial Ports
– 10/100 Mb/s Ethernet MAC (EMAC)
– One 64-Bit General-Purpose Timer
– One 64-bit General-Purpose/Watchdog Timer
– Three Enhanced Pulse Width Modulators
– Three 32-Bit Enhanced Capture Modules
• Applications
– Industrial Automation
– Home Automation
– Test and Measurement
– Portable Data Terminals
– Educational Consoles
– Power Protection Systems
• 375/456-MHz ARM926EJ-S™ RISC Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– Single Cycle MAC
– ARM^® Jazelle^® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• 128K-Byte RAM Memory
• 3.3V LVCMOS IOs (except for USB interfaces)
• Two External Memory Interfaces:
– EMIFA
• NOR (8-/16-Bit-Wide Data)
• NAND (8-/16-Bit-Wide Data)
• 16-Bit SDRAM With 128MB Address
Space
– EMIFB
• 32-Bit or 16-Bit SDRAM With 256MB
Address Space
• Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPI) Each
With One Chip-Select
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Realtime
Unit (PRU) Cores
• 32-Bit Load/Store RISC architecture
• 4K Byte instruction RAM per core
• 512 Bytes data RAM per core
• PRU Subsystem (PRUSS) can be disabled
via software to save power
– Standard power management mechanism
• Clock gating
• Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
• Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
• Two Master/Slave Inter-Integrated Circuit (I²C
Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited.
2
ARM, Jazelle are registered trademarks of ARM Limited.
3
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright © 2010, Texas Instruments Incorporated