AM1707_1008 Datasheet, PDF (144/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
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6.22.2 LCD Raster Mode
Table 6-84. LCD Raster Mode Timing
See Figure 6-55 through Figure 6-59
No.
PARAMETER
1
t_{c(PIXEL_CLK)}
2
t_{w(PIXEL_CLK_H)}
3
t_{w(PIXEL_CLK_L)}
4 t_{d(LCD_D_V)}
5
t_{d(LCD_D_IV)}
6
t_{d(LCD_AC_ENB_CS_A)}
7
t_{d(LCD_AC_ENB_CS_I)}
8
t_{d(LCD_VSYNC_A)}
9
t_{d(LCD_VSYNC_I)}
10 t_{d(LCD_HSYNC_A)}
11 t_{d(LCD_HSYNC_I)}
Cycle time, pixel clock
Pulse duration, pixel clock high
Pulse duration, pixel clock low
Delay time, LCD_PCLK↑ to LCD_D[15:0] valid (write)
Delay time, LCD_PCLK↑ to LCD_D[15:0] invalid (write)
Delay time, LCD_PCLK↓ to LCD_AC_ENB_CS↑
Delay time, LCD_PCLK↓ to LCD_AC_ENB_CS↓
Delay time, LCD_PCLK↓ to LCD_VSYNC↑
Delay time, LCD_PCLK↓ to LCD_VSYNC↓
Delay time, LCD_PCLK↑ to LCD_HSYNC↑
Delay time, LCD_PCLK↑ to LCD_HSYNC↓
(1) S2 = SYSCLK2 cycle time in ns
MIN
26.6
10
10
0
0
S2 + 0 ⁽¹⁾
S2 + 0 ⁽¹⁾
0
0
0
0
MAX
12
12
S2 + 12 ⁽¹⁾
S2 + 12 ⁽¹⁾
12
12
12
12
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
• Vertical front porch (VFP)
• Vertical sync pulse width (VSW)
• Vertical back porch (VBP)
• Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
• Horizontal front porch (HFP)
• Horizontal sync pulse width (HSW)
• Horizontal back porch (HBP)
• Pixels per panel (PPL)
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
• AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 6-55. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
144 Peripheral Information and Electrical Specifications
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