AM1707_1008 Datasheet, PDF (136/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
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6.22.1 LCD Interface Display Driver (LIDD Mode)
No.
16 t_{su(LCD_D)}
17 t_{h(LCD_D)}
Table 6-82. LCD LIDD Mode Timing Requirements
PARAMETER
Setup time, LCD_D[15:0] valid before LCD_CLK (SYSCLK2) ↑
Hold time, LCD_D[15:0] valid after LCD_CLK (SYSCLK2) ↑
MIN
MAX UNIT
7
ns
0
ns
No. PARAMETER
4 t_{d(LCD_D_V)}
5 t_{d(LCD_D_I)}
6 t_{d(LCD_E_A})
7 t_{d(LCD_E_I)}
8 t_{d(LCD_A_A)}
9 t_{d(LCD_A_I)}
10 t_{d(LCD_W_A)}
11 t_{d(LCD_W_I)}
12 t_{d(LCD_STRB_A)}
13 t_{d(LCD_STRB_I)}
14 t_{d(LCD_D_Z)}
15 t_{d(Z_LCD_D)}
1
2
3
LCD_CLK
(SYSCLK2)
LCD_D[15:0]
LCD_PCLK
LCD_VSYNC
LCD_HSYNC
LCD_AC_ENB_CS
Table 6-83. LCD LIDD Mode Timing Characteristics
MIN
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_D[15:0] valid (write)
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_D[15:0] invalid (write)
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_AC_ENB_CS↓
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_AC_ENB_CS↑
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_VSYNC↓
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_VSYNC↑
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_HSYNC↓
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_HSYNC↑
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_PCLK↑
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_PCLK↓
0
Delay time, LCD_CLK (SYSCLK2) ↑ to LCD_D[15:0] in 3-state
0
Delay time, LCD_CLK (SYSCLK2) ↑ to 15 td(Z_LCD_D) 3-state) LCD_D[15:0]
(valid from 3-state)
0
MAX
7
7
7
7
7
7
7
7
7
7
7
7
W_SU
(0 to 31)
W_STROBE
(1 to 63)
CS_DELAY
(0 to 3)
W_HOLD
(1 to 15)
R_SU
(0 to 31)
R_STROBE
(1 to 63)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
Write Data
10
12
5
11
13
14
17
16
Read Status
8
12
13
15
Data[7:0]
Not Used
9
RS
R/W
E0
E1
Figure 6-47. Character Display HD44780 Write
136 Peripheral Information and Electrical Specifications
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