AM1707_1008 Datasheet, PDF (171/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
Table 6-100. Switching Characteristics for Host-Port Interface Cycles^{(1) (2) (3)}
No.
PARAMETER
MIN
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can be
either first or second half-word)
Case 2: HPIA write following a PREFETCH
command (can be either first or second
half-word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second
half-word)
Case 4: HPIA write and Write FIFO not
empty
5
t_{d(HSTBL-HRDYV)}
Delay time, HSTROBE low to
HRDY valid
For HPI Read, HRDY can go high (not
ready) for these HPI Read conditions:
Case 1: HPID read (with auto-increment)
and data not in Read FIFO (can only
happen to first half-word of HPID access)
Case 2: First half-word access of HPID
Read without auto-increment
For HPI Read, HRDY stays low (ready) for
these HPI Read conditions:
Case 1: HPID read with auto-increment and
data is already in Read FIFO (applies to
either half-word of HPID access)
Case 2: HPID read without auto-increment
and data is already in Read FIFO (always
applies to second half-word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
5a t_{d(HASL-HRDYV)}
Delay time, HAS low to HRDY valid
6
t_{en(HSTBL-HDLZ)}
Enable time, HD driven from HSTROBE low
2
7
t_d(HRDYL-HDV)
Delay time, HRDY low to HD valid
8
t_{oh(HSTBH-HDV)}
Output hold time, HD valid after HSTROBE high
1.5
14 t_{dis(HSTBH-HDHZ)} Disable time, HD high-impedance from HSTROBE high
15 t_d(HSTBL-HDV)
Delay time, HSTROBE low to HD
valid
For HPI Read. Applies to conditions where
data is already residing in HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read with
auto-increment and data is already in Read
FIFO
Case 3: Second half-word of HPID read with
or without auto-increment
18 t_{d(HSTBH-HRDYV)}
Delay time, HSTROBE high to
HRDY valid
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: HPID write when Write FIFO is full
(can happen to either half-word)
Case 2: HPIA write (can happen to either
half-word)
Case 3: HPID write without auto-increment
(only happens to second half-word)
(1) M=SYSCLK2 period (CPU clock frequency)/2 in ns.
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
MAX
10
10
0
10
15
12
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
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Peripheral Information and Electrical Specifications 171
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