AM1707_1008 Datasheet, PDF (20/199 Pages) Texas Instruments – ARM Microprocessor

AM1707
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
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Table 3-7. External Memory Interface B (EMIFB) Terminal Functions (continued)
SIGNAL NAME
EMB_A[4]/GP7[6]
EMB_A[3]/GP7[5]
EMB_A[2]/GP7[4]
EMB_A[1]/GP7[3]
EMB_A[0]/GP7[2]
EMB_BA[1]/GP7[0]
EMB_BA[0]/GP7[1]
EMB_CLK
EMB_SDCKE
EMB_WE
EMB_RAS
EMB_CAS
EMB_CS[0]
EMB_WE_DQM[3]
EMB_WE_DQM[2]
EMB_WE_DQM[1] /GP5[14]
EMB_WE_DQM[0] /GP5[15]
PIN No.
ZKB
D11
A10
B10
C10
D10
B9
C9
C14
C13
K15
TYPE ⁽¹⁾
O
O
O
O
O
O
O
O
I/O
O
A8
O
L13
O
D9
O
A12
O
B13
O
C15
O
K14
O
PULL ⁽²⁾
MUXED
DESCRIPTION
IPD
IPD
IPD
IPD
GPIO
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
GPIO
IPU
EMIFB SDRAM row/column
address.
EMIFB SDRAM bank address.
EMIF SDRAM clock.
EMIFB SDRAM clock enable.
EMIFB write enable
EMIFB SDRAM row address
strobe.
EMIFB column address strobe.
EMIFB SDRAM chip select 0.
EMIFB write enable/data mask
for EMB_D.
3.6.6 Serial Peripheral Interface Modules (SPI0, SPI1)
Table 3-8. Serial Peripheral Interface (SPI) Terminal Functions
SIGNAL NAME
PIN
No.
ZKB
TYPE ⁽¹⁾
PULL ⁽²⁾
MUXED
DESCRIPTION
SPI0
SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
N4
I/O
IPU
UART0, EQEP0B,
GPIO, BOOT
SPI0 chip select.
SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
R5
I/O
IPU
UART0, EQEP0A,
GPIO, BOOT
SPI0 enable.
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
T5
I/O
IPD eQEP1, GPIO, BOOT SPI0 clock.
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
P6
I/O
R6
I/O
IPD
SPI0 data
slave-in-master-out.
eQEP0, GPIO, BOOT
IPD
SPI0 data
slave-out-master-in.
SPI1
SPI1_SCS[0] /UART2_TXD/GP5[13]
SPI1_ENA /UART2_RXD/GP5[12]
P4
I/O
R4
I/O
IPU
UART2, GPIO
IPU
SPI1 chip select.
SPI1 enable.
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
T6
I/O
IPD eQEP1, GPIO, BOOT SPI1 clock.
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
N5
I/O
P5
I/O
IPU
SPI1 data
slave-in-master-out.
I2C1, GPIO, BOOT
IPU
SPI1 data
slave-out-master-in.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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