DS90UH927Q Datasheet, PDF (9/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)
Symbol
Parameter
Conditions
Pin/Freq. Min Typ Max
FPD-Link LVDS INPUT
t_RSP
Receiver Strobe Position
Figure 4
RxCLKIN±, 0.25 0.5 0.75
RXIN[3:0]±
FPD-Link III CML I/O
t_LHT
CML Output Low-to-High
Transition Time
Figure 3
t_HLT
CML Output High-to-Low
Transition Time
DOUT+,
DOUT-
100 140
100 140
t_PLD
Figure 5, (Note 6)
PCLK =
Serializer PLL Lock Time
5MHz to
5
85MHz
t_SD
Delay — Latency
Figure 6
Checkerboard Pattern
Output Total Jitter,
PCLK = 5MHz
t_TJIT
Bit Error Rate ≤1E-9
Figure 8
Figure 7, (Note 12, Note 11, Checkerboard Pattern
Note 8, Note 7)
PCLK = 85MHz
Figure 8
RxCLKIN±
146*T
0.17 0.2
0.26 0.29
t_IJIT
f/40 < Jitter Freq < f/20, DES
Input Jitter Tolerance, Bit Error
Rate ≤1E-9
= DS90UH926Q
f/40 < Jitter Freq < f/20, DES
RxCLKIN±, f
= 78MHz
0.6
(Note 7, Note 10)
0.5
= DS90UH928Q
I2S Receiver
T_I2S
I2S Clock Period
RxCLKIN± f=5MHz to 85MHz I2S_CLK,
Figure 10, (Note 8, Note 16)
PCLK =
5MHz to
85MHz
>4/
PCLK
or >77
T_HC
I2S Clock High Time
Figure 10, (Note 16)
I2S_CLK 0.35
T_LC
I2S Clock Low Time
Figure 10, (Note 16)
I2S_CLK 0.35
t_sr
I2S Set-up Time
I2S_WC 0.2
I2S_D
[A,B,C,D]
t_htr
I2S Hold Time
I2S_WC 0.2
I2S_D
[A,B,C,D]
Other I/O
t_GPIO,FC
GPIO Pulse Width, Forward
Channel
GPIO[3:0],
PCLK =
5MHz to
85MHz
>2/
PCLK
t_GPIO,BC
GPIO Pulse Width, Back
Channel
GPIO[3:0]
20
Units
UI
ps
ps
ms
ns
UI
UI
UI
UI
ns
T_I2S
T_I2S
T_I2S
T_I2S
s
µs
Copyright © 1999-2012, Texas Instruments Incorporated
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