DS90UH927Q Datasheet, PDF (17/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
LVDS clock input to RxCLKIN± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods
high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL pin or by Register (Table 5).
FIGURE 12. FPD-Link Mapping: LSBs on RxIN3 (MAPSEL=L)
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FIGURE 13. FPD-Link Mapping: MSBs on RxIN3 (MAPSEL=H)
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VIDEO CONTROL SIGNALS
The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations relative to the video
pixel clock period (PCLK). By default, the DS90UH927Q applies a minimum pulse width filter on these signals to help eliminate
spurious transitions.
Normal Mode Control Signals (VS, HS, DE) have the following restrictions:
• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register
bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table
5. HS can have at most two transitions per 130 PCLKs.
Copyright © 1999-2012, Texas Instruments Incorporated
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