DS90UH927Q Datasheet, PDF (3/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
Pin Name
Pin #
I/O, Type Description
GPIO[1:0]
40, 39
I/O,
General Purpose I/O
LVCMOS See Table 1
w/ pull down
REPEAT
21
I, LVCMOS Repeater Mode Select
w/ pull down REPEAT = 0, Repeater Mode disabled (Default)
REPEAT = 1, Repeater Mode enabled
Requires a 10kΩ pull-up if set HIGH
BKWD
22
I, LVCMOS Backward Compatible Mode Select
w/ pull down BKWD = 0, interfacing to DS90UH926/8Q (Default)
BKWD = 1, interfacing to DS90UR906/8Q, DS90UR916Q
Requires a 10kΩ pull-up if set HIGH
MAPSEL
23
I, LVCMOS FPD-Link Input Map Select
w/ pull down MAPSEL = 0, LSBs on RxIN3± (Default)
MAPSEL = 1, MSBs on RxIN3±
See Figure 12and Figure 13
Requires a 10kΩ pull-up if set HIGH
LFMODE
25
I, LVCMOS Low Frequency Mode Select
w/ pull down _{LFMODE = 0, 15MHz ≤ RxCLKIN ≤ 85MHz (Default)}
LFMODE = 1, 5MHz ≤ RxCLKIN < 15MHz
Requires a 10kΩ pull-up if set HIGH
Optional Parallel Interface
GPIO[3:2]
6, 5
I/O,
General Purpose I/O
LVCMOS Shared with I2S_DD and I2S_DC
w/ pull down See Table 1
GPIO_REG
[8:5]
2, 1, 3, 4
I/O,
Register-Only General Purpose I/O
LVCMOS Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
w/ pull down See Table 2
Control and Configuration
PDB
SCL
18
I, LVCMOS Power-down Mode Input Pin
w/ pull-down Must be driven or pulled up to V_DD33. Refer to “Power Up Requirements and PDB Pin" in
the Applications Information Section.
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL
is shutdown, and I_DD is minimized. Control Registers are RESET.
9
I/O,
I2C Clock Input / Output Interface
LVCMOS Must have an external pull-up to V_DD33. DO NOT FLOAT.
Open Drain _{Recommended pull-up: 4.7kΩ.}
SDA
10
I/O,
I2C Data Input / Output Interface
LVCMOS Must have an external pull-up to V_DD33. DO NOT FLOAT.
Open Drain _{Recommended pull-up: 4.7kΩ.}
IDx
11
I, Analog I2C Address Select
External pull-up to V_DD33 is required under all conditions. DO NOT FLOAT.
Connect to external pull-up to V_DD33 and pull-down to GND to create a voltage divider.
See Figure 23and Table 4
Status
INTB
27
O, LVCMOS HDCP Interrupt
Open Drain INTB = H, normal
INTB = L, Interrupt request
FPD-Link III Serial Interface
Recommended pull-up: 4.7kΩ to V_DDIO. DO NOT FLOAT.
DOUT+
17
I/O, LVDS True Output
The output must be AC-coupled with a 0.1µF capacitor.
Copyright © 1999-2012, Texas Instruments Incorporated
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