DS90UH927Q Datasheet, PDF (48/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
ADD
(dec)
192
ADD Register
(hex) Name
0xC0 HDCP DBG
Bit(s)
7:4
3
2
1
0
Register
Type
RW
RW
RW
RW
Default
(hex)
0x00
Function Description
Reserved
RGB
CHKSUM
Enable RGB video line checksum
Enables sending of ones-complement checksum
for each 8-bit RGB data channel following end of
each video data line
Fast LV
Fast Link Verification
HDCP periodically verifies that the HDCP
Receiver is correctly synchronized. Setting this bit
will increase the rate at which synchronization is
verified. When set to a 1, Pj is computed every 2
frames and Ri is computed every 16 frames. When
set to a 0, Pj is computed every 16 frames and Ri
is computed every 128 frames.
TMR
Timer Speedup
Speed Up Speed up HDCP authentication timers.
HDCP I2C HDCP I2C Fast Mode Enable
Fast
Setting this bit to a 1 will enable the HDCP I2C
Master in the HDCP Receiver to operate with Fast
mode timing. If set to a 0, the I2C Master will
operate with Standard mode timing. This bit is
mirrored in the IND_STS register
48
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