DS90UH927Q Datasheet, PDF (55/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
POWER UP REQUIREMENTS AND PDB PIN
The power supply ramp (V_DD33 and V_DDIO) should be faster than 1.5ms with a monotonic rise. A large capacitor on the PDB pin is
needed to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled
up to V_DD33, a 10kΩ pull-up and a >10μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be
driven until both V_DD33 and V_DDIO has reached steady state. Pins VDD33_A and VDD33_B should both be externally connected,
bypassed, and driven to the same potential (they are not internally connected).
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS serializer and deserializer devices should be designed to provide low-noise power
to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray
noise, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mil) for
power / ground sandwiches. This arrangement utilizes the plane capacitance for the PCB power system and has low-inductance,
which has proven effectiveness especially at high frequencies, and makes the value and placement of external bypass capacitors
less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use
values in the range of 0.01μF to 10μF. Tantalum capacitors may be in the 2.2μF to 10μF range. The voltage rating of the tantalum
capacitors should be at least 5X the power supply voltage being used.
MLCC surface mount capacitors are recommended due to their smaller parasitic properties. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommended at the point of power entry. This is
typically in the 50μF to 100μF range and will smooth low frequency switching noise. It is recommended to connect power and
ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the
capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body
size X7R chip capacitor, such as 0603 or 0805, is recommended for external bypass. A small body sized capacitor has less
inductance. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of
20MHz-30MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply
rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to
the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables
typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many
be used to provide clean power to sensitive circuits such as PLLs. For DS90UH927Q, only one common ground plane is required
to connect all device related ground pins.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS lines to prevent
coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100Ω are typically recommended for LVDS
interconnect. The closely coupled lines help to ensure that coupled noise will appear as common mode and thus is rejected by the
receivers. The tightly coupled lines will also radiate less.
At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device ground to the PCB
ground plane, as well as conduct heat from the exposed pad of the package to the PCB ground plane. More information on the
LLP style package, including PCB design and manufacturing requirements, is provided in TI Application Note: AN-1187.
CML INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instruments web
site at: http://www.ti.com/lit/ml/snla187/snla187.pdf
Copyright © 1999-2012, Texas Instruments Incorporated
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