DS90UH927Q Datasheet, PDF (18/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is
130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register
bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table
5. DE can have at most two transitions per 130 PCLKs.
EMI REDUCTION FEATURES
LVCMOS V_DDIO OPTION
The 1.8V or 3.3V LVCMOS inputs and outputs are powered from separate VDDIO supply pins to offer compatibility with external
system interface signals. Note: When configuring the V_DDIO power supplies, all the single-ended control input pins for device need
to scale together with the same operating V_DDIO levels. If V_DDIO is selected to operate in the 3.0V to 3.6V range, V_DDIO must be
operated within 300mV of V_DD33.
POWER DOWN (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an external device,
or through V_DDIO, where V_DDIO = 3.0V to 3.6V or V_DD33. To save power, disable the link when the display is not needed (PDB =
LOW). Ensure that this pin is not driven HIGH before V_DD33 and V_DDIO have reached final levels. When PDB is driven low, ensure
that the pin is driven to 0V for at least 1.5ms before releasing or driving high. In the case where PDB is pulled up to V_DDIO = 3.0V
to 3.6V or V_DD33 directly, a 10kΩ pull-up resistor and a >10µF capacitor to ground are required (See Figure 27).
Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time, PDB must be held
low for a minimum period of time. See AC Electrical Characteristics for more information.
REMOTE AUTO POWER DOWN MODE
The DS90UH927Q serializer features a Remote Auto Power Down mode. This feature is enabled and disabled through the register
bit 0x01[7] (Table 5). When the back channel is not detected, either due to an idle or powered-down deserializer, the serializer
enters remote auto power down mode. Power dissipation of the serializer is significantly reduced in this mode. The serializer
automatically attempts to resume normal operation upon detection of an active back channel from the deserializer. To complete
the wake-up process and reactivate forward channel operation, the remote power-down feature must be disabled by either a local
I2C host, or by an auto-ACK I2C transaction from a remote I2C host located at the deserializer. The Remote Auto Power Down
Sleep/Wake cycle is shown below in Figure 14:
FIGURE 14. Remote Auto Power Down Sleep/Wake Cycle
30193009
To resume normal operation, the Remote Auto Power Down feature must be disabled in the device control register. This may be
accomplished from a local I2C controller by writing reg_0x01[7]=0 (Table 5). To disable from a remote I2C controller located at the
deserializer, perform the following procedure to complete the wake-up process:
1. Power up remote deserializer (back channel must be active)
2. Enable I2C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=1
3. Enable I2C AUTO ACK by setting deserializer register reg_0x03[2]=1
4. Disable Remote Auto Power Down by setting serializer register reg_0x01[7]=0
5. Disable I2C AUTO ACK by setting deserializer register reg_0x03[2]=0
18
Copyright © 1999-2012, Texas Instruments Incorporated