DS90UH927Q Datasheet, PDF(11/59 Page) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH927Q Datasheet, PDF (11/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH927Q

Note 1: âAbsolute Maximum Ratingsâ indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or

specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: Typical values represent most likely parametric norms at VDD33 = 3.3V, VDDIO = 1.8V or 3.3V, Ta = +25 degC, and at the Recommended Operation

Conditions at the time of product characterization and are not guaranteed.

Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and

ÎVOD, which are differential voltages.

Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured

at the device VDD33 and VDDIO pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise

frequency is less than 50MHz.

Note 5: Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDD33 and VDDIOsupplies with amplitude =

100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when

the noise frequency on the Ser is less than 50MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

Note 6: tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.

Note 7: Specification is guaranteed by characterization and is not tested in production

Note 8: Specification is guaranteed by design and is not tested in production

Note 9: tTJIT (@BER of 1E-9) specifies the allowable jitter on RxCLKINÂ±

Note 10: Jitter Frequency is specified in conjunction with DS90UH928Q PLL bandwidth.

Note 11: UI â Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency.

Note 12: Output jitter specs are dependent upon the input clock jitter at the SER

Note 13: The DS90UH927Q VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5ms with

a monotonic rise

â¥ Note 14: PDB is specified to 3.3V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO 3.0V

Note 15: IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500ms or part damage may result

Note 16: I2S specifications for tLC and tHC pulses must each be greater than 2 PCLK periods to guarantee sampling and supersedes the 0.35*TI2S_CLK requirement.

tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK

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