DS90UH927Q Datasheet, PDF (16/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
Functional Description
The DS90UH927Q converts a FPD-Link interface (4 LVDS data channels + 1 LVDS Clock) to a FPD-Link III interface. This device
transmits a 35-bit symbol over a single serial pair operating at up to a 2.975Gbps line rate. The serial stream contains an embedded
clock, video control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal quality and support
AC coupling.
The DS90UH927Q applies encryption to the video data using a High-Bandwidth Digital Content Protection (HDCP) Cipher, and
transmits the encrypted data out through the FPD-Link III interface. Audio encryption is supported. On chip non-volatile memory
stores the HDCP keys. All key exchanges are conducted over the FPD-Link III bidirectional control interface.
The DS90UH927Q serializer is intended for use with a DS90UH928Q or DS90UH926Q deserializer, but is also backward com-
patible with DS90UR906Q, DS90UR908Q, DS90UR910Q, and DS90UR916Q FPD-Link II deserializers.
The DS90UH927Q serializer and DS90UH928Q or DS90UH926Q deserializer incorporate an I2C compatible interface. The I2C
compatible interface allows programming of serializer or deserializer devices from a local host controller. In addition, the devices
incorporate a bidirectional control channel (BCC) that allows communication between serializer/deserializer as well as remote I2C
slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward channel (serializer to
deserializer) combined with lower speed signaling in the reverse channel (deserializer to serializer). Through this interface, the
BCC provides a mechanism to bridge I2C transactions across the serial link from one I2C bus to another. The implementation
allows for arbitration with other I2C compatible masters at either side of the serial link.
HIGH SPEED FORWARD CHANNEL DATA TRANSFER
The High Speed Forward Channel is composed of a 35-bit frame containing RGB data, sync signals, HDCP, I2C, and I2S audio
transmitted from Serializer to Deserializer. Figure 11 illustrates the serial stream generated per PCLK cycle into RxCLKIN±. This
data payload is optimized for signal transmission over an AC coupled link. Data is randomized, DC-balanced and scrambled.
FIGURE 11. FPD-Link III Serial Stream
30193007
The device supports pixel clock ranges of 5MHz to 15MHz (LFMODE=1) and 15MHz to 85MHz (LFMODE=0). This corresponds
to an application payload rate range of 155Mbps to 2.635Gbps, with an actual line rate range of 525Mbps to 2.975Gbps.
LOW SPEED BACK CHANNEL DATA TRANSFER
The Low-Speed Back Channel of the DS90UH927Q provides bidirectional communication between the display and host processor.
Data is transferred simultaneously over the same physical link as the high-speed forward channel data. The back channel transports
I2C, HDCP, CRC, and 4 bits of standard GPIO information with a 10Mbps line rate.
BACKWARD COMPATIBLE MODE
The DS90UH927Q is also backward compatible to DS90UR906Q, DS90UR908Q FPD, and DS90UR916Q FPD-Link II deserializers
for PCLK frequencies ranging from 5MHz to 65MHz. It is also backward compatible with the DS90UR910Q for PCLK frequencies
ranging from 5MHz to 75MHz. The serializer transmits 28-bits of data over a single serial FPD-Link II pair operating at a payload
rate of 120Mbps to 1.8Gbps, corresponding to a line rate of 140Mbps to 2.1Gbps. The Backward Compatibility configuration can
be selected through the BKWD pin or programmed through the configuration register (Table 5). The bidirectional control channel,
HDCP, bidirectional GPIOs, I2S, and interrupt (INTB) are not active in this mode. However, local I2C access to the serializer is still
available. Note: PCLK frequency range in this mode is 15MHz to 75MHz for LFMODE=0 and 5MHZ to <15MHz for LFMODE=1.
COMMON MODE FILTER PIN (CMF)
The serializer provides access to the center tap of the internal CML termination. A 0.1μF capacitor must be connected from this
pin to GND for additional common-mode filtering of the differential pair (Figure 27). This increases noise rejection capability in high-
noise environments.
FPD-LINK INPUT FRAME AND COLOR BIT MAPPING SELECT
The DS90UH927Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs on RxIN[3]±,
shown in Figure 12, or MSBs on RxIN[3], shown in Figure 13. Each frame corresponds to a single pixel clock (PCLK) cycle. The
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