DS90UH927Q Datasheet, PDF (29/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
Serial Control Bus
The DS90UH927Q may also be configured by the use of a I2C compatible serial control bus. Multiple devices may share the serial
control bus (up to 10 device addresses supported). The device address is set via a resistor divider (R1 and R2 — see Figure 23
below) connected to the IDx pin.
FIGURE 23. Serial Control Bus Connection
30193001
The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial Bus Data Input /
Output signal. Both SCL and SDA signals require an external pull-up resistor to V_DD33 or V_DDIO = 3.0V to 3.6V. For most applications,
a 4.7kΩ pull-up resistor to V_DD33 is recommended. However, the pull-up resistor value may be adjusted for capacitive loading and
data rate requirements. The signals are either pulled High, or driven Low.
The IDx pin configures the control interface to one of 10 possible device addresses. A pull-up resistor and a pull-down resistor may
be used to set the appropriate voltage ratio between the IDx input pin (V_R2) and V_DD33, each ratio corresponding to a specific device
address. See Table 5 below.
TABLE 4. Serial Control Bus Addresses for IDx
Ideal Ratio
#
V_R2 / V_DD33
1
0
2
0.306
3
0.350
4
0.393
5
0.440
6
0.483
7
0.529
8
0.572
9
0.618
10
0.768
Ideal V_R2
(V)
0
1.011
1.154
1.298
1.452
1.594
1.745
1.887
2.040
2.535
Suggested
Resistor R1 kΩ
(1% tol)
Open
221
210
196
182
169
147
143
121
90.9
Suggested
Resistor R2 kΩ
(1% tol)
40.2 or >10
97.6
113
127
143
158
165
191
196
301
Address 7'b
0x0C
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
Address 8'b
0x18
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x36
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions
Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 24 belowFigure 24
Copyright © 1999-2012, Texas Instruments Incorporated
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