DS90UH927Q Datasheet, PDF (28/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL)
16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL
17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the auto-scrolling feature
Additionally, the Pattern Generator incorporates one user-configurable full-screen 24-bit color, which is controlled by the PGRS,
PGGS, and PGBS registers. This is pattern #14. One of the pattern options is statically selected in the PGCTL register when Auto-
Scrolling is disabled. The PGTSC and PGTSO1-8 registers control the pattern selection and order when Auto-Scrolling is enabled.
COLOR MODES
By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue outputs are enabled.
18-bit color mode can be activated from the configuration registers (Table 5). In 18-bit mode, the 6 most significant bits (bits 7-2)
of the Red, Green, and Blue outputs are enabled; the 2 least significant bits will be 0.
VIDEO TIMING MODES
The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern Generator detects
the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not present on VS, the Pattern Generator
determines Vertical Blank by detecting when the number of inactive pixel clocks (DE = 0) exceeds twice the detected active line
length. In internal timing mode, the Pattern Generator uses custom video timing as configured in the control registers. The internal
timing generation may also be driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal
timing with External Clock are enabled by the control registers (Table 5).
EXTERNAL TIMING
In external timing mode, the Pattern Generator passes the incoming DE, HS, and VS signals unmodified to the video control outputs
after a two pixel clock delay. It extracts the active frame dimensions from the incoming signals in order to properly scale the
brightness patterns. If the incoming video stream does not use the VS signal, the Pattern Generator determines the Vertical Blank
time by detecting a long period of pixel clocks without DE asserted.
PATTERN INVERSION
The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes the output pattern
to be bitwise-inverted. For example, the full screen Red pattern becomes full-screen cyan, and the Vertically Scaled Black to Green
pattern becomes Vertically Scaled White to Magenta.
AUTO SCROLLING
The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of enabled pattern types.
A sequence of up to 16 patterns may be defined in the registers. The patterns may appear in any order in the sequence and may
also appear more than once.
ADDITIONAL FEATURES
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It consists of the
Pattern Generator Indirect Address (PGIA reg_0x66 — Table 5) and the Pattern Generator Indirect Data (PGID reg_0x67 — Table
5). See TI application Note AN-2198.
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