DS90UH927Q Datasheet, PDF (20/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
The input value present on GPIO[3:0] may also be read from register, or configured to local output mode (Table 5).
GPIO[8:5]
GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local register bits only.
Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into REG_GPIO mode. See Table 2 for
GPIO enable and configuration.
Note: Local GPIO value may be configured and read either through local register access, or remote register access through the
Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not transported from serializer to deserializer
as is the case for GPIO[3:0].
Description
GPIO_REG8
GPIO_REG7
GPIO_REG6
GPIO_REG5
GPIO3
GPIO2
GPIO1
GPIO0
TABLE 2. GPIO_REG and GPIO Local Enable and Configuration
Register Configuration
0x11 = 0x01
0x11 = 0x09
0x11 = 0x03
0x10 = 0x01
0x10 = 0x09
0x10 = 0x03
0x10 = 0x01
0x10 = 0x09
0x10 = 0x03
0x0F = 0x01
0x0F = 0x09
0x0F = 0x03
0x0F = 0x01
0x0F = 0x09
0x0F = 0x03
0x0E = 0x01
0x0E = 0x09
0x0E = 0x03
0x0E = 0x01
0x0E = 0x09
0x0E = 0x03
0x0D = 0x01
0x0D = 0x09
0x0D = 0x03
Function
Output, L
Output, H
Input, Read: 0x1D[0]
Output, L
Output, H
Input, Read: 0x1C[7]
Output, L
Output, H
Input, Read: 0x1C[6]
Output, L
Output, H
Input, Read: 0x1C[5]
Output, L
Output, H
Input, Read: 0x1C[3]
Output, L
Output, H
Input, Read: 0x1C[2]
Output, L
Output, H
Input, Read: 0x1C[1]
Output, L
Output, H
Input, Read: 0x1C[0]
I2S AUDIO INTERFACE
The DS90UH927Q serializer features six I2S input pins that, when paired with a DS90UH928Q deserializer, supports surround
sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1MHz and the smaller of <PCLK/2 or <13MHz.
Four I2S data inputs transport two channels of I2S-formatted digital audio each, with each channel delineated by the word select
(I2C_WC) input. I2S audio transport is not available in Backwards Compatibility Mode (BKWD = 1).
FIGURE 15. I2S Connection Diagram
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