DS90UH927Q Datasheet, PDF (54/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
Applications Information
DISPLAY APPLICATION
The DS90UH927Q, in conjunction with the DS90UH928Q or DS90UH926Q, is intended for interface between a HDCP compliant
host (graphics processor) and a display supporting 24-bit color depth (RGB888) and high definition (720p) digital video format. It
can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz together with three control bits (VS, HS and DE) and four
I2S audio streams. The included HDCP 1.3 compliant cipher block allows the authentication of the HDCP Deserializer, which
decrypts both video and audio contents. The HDCP keys are pre-loaded by TI into Non-Volatile Memory (NVM) for maximum
security.
TYPICAL APPLICATION CONNECTION
Figure 27 shows a typical application of the DS90UH927Q serializer for an 85 MHz 24-bit Color Display Application. The 5 LVDS
input pairs require external 100Ω terminations. The CML outputs must have an external 0.1µF AC coupling capacitor on the high
speed serial lines. The serializer has internal CML termination on its high speed outputs.
Bypass capacitors should be placed near the power supply pins. At a minimum, four (4) 4.7µF capacitors should be used for local
device bypassing. Ferrite beads are placed on the two sets of supply pins (VDD33 and VDDIO) for effective noise suppression.
The interface to the graphics source is LVDS. The VDDIO pins may be connected to 3.3V or 1.8V. A capacitor and resistor are
placed on the PDB pin to delay the enabling of the device until power is stable.
FIGURE 27. Typical Connection Diagram
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