DS90UH927Q Datasheet, PDF (53/59 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927Q
ADD
(dec)
208
ADD Register
(hex) Name
0xD0 IND STS
209 0xD1 IND SAR
210 0xD2 IND OAR
211 0xD3 IND DATA
240 0xF0 HDCP TX ID
241 0xF1
242 0xF2
243 0xF3
244 0xF4
245 0xF5
Bit(s)
7
6
5
4
3:2
1
0
7:1
0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Register
Type
RW
RW
RW
R
R
RW
RW
RW
RW
R
R
R
R
R
R
Default
(hex)
0x00
0x00
0x00
0x00
0x5F
0x55
0x48
0x39
0x32
0x37
Function Description
IA Reset
Indirect Access Reset
Setting this bit to a 1 will reset the I2C Master in
the HDCP Receiver. As this may leave the I2C bus
in an indeterminate state, it should only be done if
the Indirect Access mechanism is not able to
complete due to an error on the destination I2C
bus.
Reserved
I2C TO
DIS
I2C Timeout Disable
Setting this bit to a 1 will disable the bus timeout
function in the I2C master. When enabled, the bus
timeout function allows the I2C master to assume
the bus is free if no signaling occurs for more than
1 second.
I2C Fast
I2C Fast mode Enable
Setting this bit to a 1 will enable the I2C Master in
the HDCP Receiver to operation with Fast mode
timing. If set to a 0 (default), the I2C Master will
operate with Standard mode timing.
Reserved
IA ACK
Indirect Access Acknowledge
The acknowledge bit indicates that a valid
acknowledge was received upon completion of
the I2C read or write to the slave. A value of 0
(default) indicates the read/write did not complete
successfully.
IA DONE
Indirect Access Done
Set to a 1 to indicate completion of Indirect
Register Access. This bit will be cleared or read or
by start of a new Indirect Register Access.
IA SADDR Indirect Access Slave Address
This field should be programmed with the slave
address for the I2C slave to be accessed
IA RW
Indirect Access Read/Write
0: Write (default)
1: Read
IA Offset
Indirect Access Offset
It is programmed with the register address for the
I2C indirect access.
IA Data
Indirect Access Data
For an indirect write, It is written with the write data.
For an indirect read, it contains the result of a
successful read.
ID0
First byte ID code, ‘_’
ID1
Second byte of ID code, ‘U’
ID2
Third byte of ID code. ‘H'
ID3
Forth byte of ID code: ‘9’
ID4
Fifth byte of ID code: “2”
ID5
Sixth byte of ID code: “7”
Copyright © 1999-2012, Texas Instruments Incorporated
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