DS90UH926QSQE Datasheet, PDF (9/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
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SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.^(1)(2)(3)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max Units
GPIO BIT RATE
Forward Channel Bit Rate
B_R
Back Channel Bit Rate
See ^{(4) (5)}
f = 5 – 85MHz,
GPIO[3:0]
>50
0.25*f
>75
Mbps
kbps
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
E_W
Differential Output Eye Opening
Width ⁽⁶⁾
R_L = 100Ω,
Jitter Freq >f / 40
CMLOUTP,
CMLOUTN,
0.3
0.4
UI
E_H
Differential Output Eye Height
Figure 3⁽⁴⁾⁽⁵⁾
f = 85MHz
200
300
mV
SWITCHING CHARACTERISTICS
t_RCP
t_RDC
t_CLH
t_CHL
t_ROS
t_ROH
PCLK Output Period
PCLK Output Duty Cycle
LVCMOS Low-to-High Transition
Time
Figure 4
LVCMOS High-to-Low Transition
Time
Figure 4
Data Valid before PCLK – Setup
Time
SSCG = OFF
Figure 7
Data Valid after PCLK – Hold
Time
SSCG = OFF
Figure 7
t_RCP = t_TCP
V_DDIO = 1.71 - 1.89V,
C_L = 12pF
V_DDIO = 3.0 – 3.6V,
C_L = 12pF
V_DDIO = 1.71 - 1.89V,
C_L = 12pF
V_DDIO = 3.0 – 3.6V,
C_L = 12pF
V_DDIO = 1.71 - 1.89V,
C_L = 12pF
V_DDIO = 3.0 – 3.6V,
C_L = 12pF
V_DDIO = 1.71 - 1.89V,
C_L = 12pF
V_DDIO = 3.0 – 3.6V,
C_L = 12pF
PCLK
11.76
T
200
ns
45
50
55
%
2
3
ns
2
R[7:0], G[7:0],
2
B[7:0], HS,
VS, DE,
PCLK, LOCK,
2
PASS, MCLK,
I2S_CLK,
2.2
I2S_WC,
I2S_DA,
I2S_DB
2.2
3.0
3
ns
3
ns
3
ns
ns
ns
ns
3.0
ns
R[7:0], G[7:0],
B[7:0]
10
ns
HS, VS, DE,
PCLK, LOCK,
15
ns
t_XZR
Active to OFF Delay
Figure 6⁽⁴⁾⁽⁵⁾
OEN = L, OSS_SEL = H
PASS
MCLK,
I2S_CLK,
I2S_WC,
60
ns
I2S_DA,
I2S_DB
t_DDLT
t_DD
Lock Time
Figure 6^{(4) (5) (7)}
Delay – Latency⁽⁴⁾⁽⁵⁾
SSCG = OFF
f = 5 – 85MHz
f = 5 – 85MHz
5
40
ms
147*T
ns
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at V_DD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
(6) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35*PCLK). The UI scales with PCLK frequency.
(7) t_DDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream.
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