DS90UH926QSQE Datasheet, PDF (29/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
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ADD
(dec)
0
ADD Register
(hex) Name
0x00 I2C Device ID
1 0x01 Reset
2 0x02 Configuration
[0]
Bit(s)
7:1
0
7
6:3
2
1
0
7
6
5
4
3
2
1
0
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
Table 9. Serial Control Bus Registers
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default Function
(hex)
Device ID
ID Setting
0x04
Remote
Auto Power
Down
BC Enable
Digital
RESET1
Digital
RESET0
0x00 Output
Enable
OEN and
OSS_SEL
Override
OSC Clock
Enable
Output
Sleep State
Select
(OSS_SEL)
Backward
Compatible
select by
pin or
register
control
Backward
Compatible
Mode
Select
LFMODE
select by
pin or
register
control
LFMODE
Descriptions
7–bit address of Deserializer
See Table 4
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
Remote Auto Power Down
1: Power down when no forward channel link is detected
0: Do not power down when no forward channel link is
detected
Reserved.
Back channel enable
1: Enable
0: Disable
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
LVCMOS Output Enable.
1: Enable
0: Disable. Tri-state Outputs
Overrides Output Enable Pin and Output State pin
1: Enable override
0: Disable - no override
OSC Clock Output Enable
If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
OSS Select to Control Output State during Lock Low
Period
1: Enable
0: Disable
Backward Compatible (BC) mode set by MODE_SEL pin
or register.
1: BC is set by register bit. Use register bit reg_0x02[2] to
set BC Mode
0: Use MODE_SEL pin.
Backward compatible (BC) mode to DS90UR905Q or
DS90UR907Q, if reg_0x02[3] = 1
1: Backward compatible with DS90UR905Q or
DS90UR907Q
(Set LFMODE = 0)
0: Backward Compatible is OFF (default)
Frequency range is set by MODE_SEL pin or register
1: Frequency range is set by register. Use register
bitreg_0x02[0] to set LFMODE
0: Frequency range is set by MODE_SEL pin.
Frequency range select
1: PCLK range = 5 - <15 MHz, if reg_0x02[1] = 1
0: PCLK range = 15 - 85 MHz (default)
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