DS90UH926QSQE Datasheet, PDF (3/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
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SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
PIN DESCRIPTIONS
Pin Name
Pin #
I/O, Type Description
LVCMOS Parallel Interface
R[7:0]
33, 34, 35, 36, O, LVCMOS RED Parallel Interface Data Output Pins
37, 39, 40, 41 w/ pull down Leave open if unused
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1
G[7:0]
20, 21, 22, 23, O, LVCMOS GREEN Parallel Interface Data Output Pins
25, 26, 27, 28 w/ pull down Leave open if unused
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
B[7:0]
9, 10, 11, 12,
14, 17, 18, 19
O, LVCMOS
w/ pull down
BLUE Parallel Interface Data Output Pins
Leave open if unused
B0 can optionally be used as GPO_REG4 and B1 can optionally be used as I2S_DB or
GPO_REG5.
HS
8
O, LVCMOS Horizontal Sync Output Pin
w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 9
VS
7
O, LVCMOS Vertical Sync Output Pin
w/ pull down Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
DE
6
O, LVCMOS Data Enable Output Pin
w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 9
PCLK
5
O, LVCMOS Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 9
w/ pull down
I2S_CLK,
I2S_WC,
I2S_DA
1, 30, 45
O, LVCMOS
w/ pull down
Digital Audio Interface Data Output Pins
Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
MCLK
60
O, LVCMOS I2S Master Clock Output. x1, x2, or x4 of I2S_CLK Frequency.
w/ pull down
Optional Parallel Interface
I2S_DB
18
O, LVCMOS Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by
w/ pull down MODE_SEL or configuration register
Leave open if unused
I2S_B can optionally be used as BI or GPO_REG5.
GPIO[3:0]
27, 28, 40, 41 I/O,
LVCMOS
w/ pull down
Standard General Purpose IOs.
Available only in 18-bit color mode, and set by MODE_SEL or configuration register.
See Table 9
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[8: 1, 30, 45, 18, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 9
4]
19
w/ pull down Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
INTB_IN
16
Input,
Interrupt Input
LVCMOS w/ Shared with BISTC
pull-down
Control
PDB
59
I, LVCMOS Power-down Mode Input Pin
w/ pull-down PDB = H, device is enabled (normal operation)
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = L, device is powered down.
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE,
the PLL is shutdown and IDD is minimized. .
OEN
31
Input, Output Enable Pin.
LVCMOS w/ See Table 3
pull-down
OSS_SEL
46
Input, Output Sleep State Select Pin.
LVCMOS w/ See Table 3
pull-down
MODE_SEL
15
I, Analog Device Configuration Select. See Table 4
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