DS90UH926QSQE Datasheet, PDF (10/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.^(1)(2)(3)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max Units
f = 5 – <15
MHz
0.5
ns
t_DCCJ
Cycle-to-Cycle Jitter⁽⁸⁾⁽⁹⁾
SSCG = OFF
f = 15 – 85
MHz
0.2
ns
I2S_CLK = 1 -
+/-2
ns
12.28MHz
t_ONS
Data Valid After OEN = H
SetupTime
Figure 8⁽⁸⁾⁽⁹⁾
VDDIO = 1.71 - 1.89V,
CL = 12pF
VDDIO = 3.0 – 3.6V,
CL = 12pF
50
ns
50
ns
Data Tri-State After OEN = L
SetupTime
VDDIO = 1.71 - 1.89V,
CL = 12pF
R[7:0], G[7:0],
50
ns
t_ONH
Figure 8⁽⁸⁾⁽⁹⁾
B[7:0], HS,
VDDIO = 3.0 – 3.6V,
CL = 12pF
VS, DE,
PCLK, MCLK,
50
ns
VDDIO = 1.71 - 1.89V,
Data Tri-State after OSS_ SEL = _{CL = 12pF}
t_SES
H, Setup Time
Figure 8⁽⁸⁾⁽⁹⁾
VDDIO = 3.0 – 3.6V,
CL = 12pF
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
5
ns
5
ns
t_SEH
VDDIO = 1.71 - 1.89V,
Data to Low after OSS_SEL = L _{CL = 12pF}
Setup Time
Figure 8⁽⁸⁾⁽⁹⁾
VDDIO = 3.0 – 3.6V,
CL = 12pF
5
ns
5
ns
BIST Mode
t_PASS
BIST PASS Valid Time
BISTEN = H
Figure 9⁽⁸⁾⁽⁹⁾
PASS
800
ns
SSCG Mode
f_DEV
f_MOD
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
SeeFigure 13, Table 1 and
Table 2⁽⁸⁾⁽⁹⁾
±0.5
f = 85MHz,
SSCG = ON
8
±2.5
%
100
kHz
(8) Specification is ensured by characterization and is not tested in production.
(9) Specification is ensured by design and is not tested in production.
10
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