DS90UH926QSQE Datasheet, PDF (38/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
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ADD
(dec)
43
44
58
65
ADD Register
(hex) Name
0x2B I2S Control
0x2C SSCG Control
0x3A I2S MCLK
Output
0x41 Link Error
Count
Table 9. Serial Control Bus Registers (continued)
Bit(s)
7
6:1
0
7:4
3
2:0
7
6:4
3:0
7:5
4
3:0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default Function
(hex)
0x00 I2S PLL
I2S Clock
Edge
0x00
SSCG
Enable
SSCG
Selection
0x00
MCLK
Override
MCLK
Frequency
Slect
0x03
Link Error
Count
Enable
Link Error
Count
Descriptions
I2S PLL Control
0: I2S PLL is ON for I2S data jitter cleaning
1: I2S PLL is OFF. No jitter cleaning
Reserved
I2S Clock Edge Select
0: I2S Data is strobed on the Rising Clock Edge
1: I2S Data is strobed on the Falling Clock Edge
Reserved
Enable Spread Spectrum Clock Generator
0: Disable
1: Enable
SSCG Frequency Deviation:
When LFMODE = H
fdev fmod
000: +/- 0.7 CLK/628
001: +/- 1.3
010: +/- 1.8
011: +/- 2.5
100: +/- 0.7 CLK/388
101: +/- 1.2
110: +/- 2.0
111: +/- 2.5
When LFMODE = L
fdev fmod
000: +/- 0.9 CLK/2168
001: +/- 1.2
010: +/- 1.9
011: +/- 2.5
100: +/- 0.7 CLK/1300
101: +/- 1.3
110: +/- 2.0
111: +/- 2.5
1: Override divider select for MCLK
0: No override for MCLK divider
See Table 5
Reserved
Reserved
Enable serial link data integrity error count
1: Enable error count
0: Disable
Link error count threshold.
Counter is pixel clock based. clk0, clk1 and DCA are
monitored for link errors, if error count is enabled,
deserializer loose lock once error count reaches threshold.
If disabled deserilizer loose lock with one error.
38
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