DS90UH926QSQE Datasheet, PDF (25/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

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DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
DS90UH926Q
R[7:0]
G[7:0]
B[7:0]
DE
VS
HS
VDD33
I2S_CLK
I2S_WC
I2S_DA
MODE_SEL
Optional
VDDIO
DS90UH925Q
R[7:0]
G[7:0]
B[7:0]
DE
VS
HS
I2S_CLK
I2S_WC
I2S_DA
MODE_SEL
VDD33
VDD33
ID[x]
INTB_IN
SDA
SCL
VDD33
INTB
SDA
SCL
VDD33
ID[x]
Figure 17. HDCP Repeater Connection Diagram
BUILT IN SELF TEST (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics.
BIST Configuration and Status
The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or
configuration register (Table 9) through the deserializer. When LFMODE = 0, the pin based configuration defaults
to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can
select the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the
pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to
35 bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 9.
Sample BIST Sequence
See Figure 18 for the BIST mode flow diagram.
Step 1: For the DS90UH925Q and DS90UH926Q FPD-Link III chipset, BIST Mode is enabled via the BISTEN
pin of DS90UH926Q FPD-Link III deserializer. The desired clock source is selected through BISTC pin.
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