DS90UH926QSQE Datasheet, PDF (16/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
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COMMON MODE FILTER PIN (CMF)
The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1 μF capacitor has to be connected to this pin to Ground.
VIDEO CONTROL SIGNAL FILTER
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 12.
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 12. Video Control Signal Filter Waveform
EMI REDUCTION FEATURES
Spread Spectrum Clock Generation (SSCG)
The DS90UH926Q provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both
clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.5% (5%
total) at up to 100 kHz modulations are available. This feature may be controlled by register. See Table 1,
Table 2 and Table 9. Note: Do not enable the SSCG feature if the source PCLK into the SER has a clock with
spread spectrum already.
Frequency
F_PCLK+
F_PCLK
F_PCLK-
fdev(max)
fdev(min)
Time
1/fmod
Figure 13. SSCG Waveform
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