DS90UH926QSQE Datasheet, PDF (20/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
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I2S RECEIVING
In normal 24-bit RGB operation mode, the DS90UH926Q provides up to 3-bit of I2S. They are I2S_CLK, I2S_WC
and I2S_DA, as well as the Master I2S Clock (MCLK). The encrypted and packetized audio information is
received during the video blanking periods along with specific information about the clock frequency. Note: The
bit rates of any I2S input bits must maintain one fourth of the PCLK rate. The audio decryption is supported per
HDCP v1.3. A jitter cleaning feature reduces I2S_CLK output jitter to +/- 2ns.
I2S Jitter Cleaning
The DS90UH926Q features a standalone PLL to clean the I2S data jitter supporting high end car audio systems.
If I2S CLK frequency is less than 1MHz, this feature has to be disabled through the register bit I2S Control
(0x2B) in Table 9.
Secondary I2S Channel
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 4) or program through the register bit (Table 9).
MCLK
The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S
PLL is disabled, the MCLK output is OFF. Table 5 below covers the range of I2S sample rates and MCLK
frequencies.
By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK frequencies can also
be enabled through the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 9. To select desired MCLK
frequency, write bit 7 (0x3A) = 1, then write to bit [6:4] accordingly.
Sample Rate (kHz)
32
44.1
48
96
192
32
44.1
48
Table 5. Audio Interface Frequencies
I2S Data Word Size
(bits)
16
16
16
16
16
24
24
24
I2S CLK
(MHz)
1.024
1.411
1.536
3.072
6.144
1.536
2.117
2.304
MCLK Output
(MHz)
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
Bit [6:4]
(Address 0x3A)
000
001
010
000
001
010
000
001
010
001
010
011
010
011
100
000
001
010
001
010
011
001
010
011
20
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