DS90UH926QSQE Datasheet, PDF (40/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
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ADD
(dec)
101
ADD Register
(hex) Name
0x65 Pattern
Generator
Configuration
102 0x66 Pattern
Generator
Indirect
Address
103 0x67 Pattern
Generator
Indirect Data
128 0x80 RX_BKSV0
129 0x81 RX_BKSV1
130 0x82 RX_BKSV2
131 0x83 RX_BKSV3
132 0x84 RX_BKSV4
144 0x90 TX_KSV0
145 0x91 TX_KSV1
146 0x92 TX_KSV2
147 0x93 TX_KSV3
148 0x94 TX_KSV4
Table 9. Serial Control Bus Registers (continued)
Bit(s)
7:5
4
3
2
1
0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Register
Type
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
R
Default Function
(hex)
0x00
Pattern
Generator
18 Bits
Pattern
Generator
External
Clock
Pattern
Generator
Timing
Select
Pattern
Generator
Color Invert
Pattern
Generator
Auto-Scroll
Enable
0x00 Indirect
Address
0x00 Indirect
Data
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
RX BKSV0
RX BKSV1
RX BKSV2
RX BKSV3
RX BKSV4
TX KSV0
TX KSV1
TX KSV2
TX KSV3
TX KSV4
Descriptions
Reserved
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns
will have 64 levels of brightness and the R, G, and B
outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use
256 levels of brightness.
Select External Clock Source
1: Selects the external pixel clock when using internal
timing.
0: Selects the internal divided clock when using internal
timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
Timing Select Control
1: The Pattern Generator creates its own video timing as
configured in the Pattern Generator Total Frame Size,
Active Frame Size. Horizontal Sync Width, Vertical Sync
Width, Horizontal Back Porch, Vertical Back Porch, and
Sync Configuration registers.
0: the Pattern Generator uses external video timing from
the pixel clock, Data Enable, Horizontal Sync, and Vertical
Sync signals.
Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the
next enabled pattern after the number of frames specified
in the Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
This 8-bit field sets the indirect address for accesses to
indirectly-mapped registers. It should be written prior to
reading or writing the Pattern Generator Indirect Data
register.
See AN-2198 (SNLA132)
When writing to indirect registers, this register contains the
data to be written. When reading from indirect registers,
this register contains the read back value.
See AN-2198 (SNLA132
BKSV0: Value of byte 0 of the Deserializer KSV
BKSV1: Value of byte 1 of the Deserializer KSV
BKSV2: Value of byte 2 of the Deserializer KSV
BKSV3: Value of byte 3of the Deserializer KSV.
BKSV4: Value of byte 4of the Deserializer KSV.
KSV0: Value of byte 0 of the Serializer KSV.
KSV1: Value of byte 1 of the Serializer KSV.
KSV2: Value of byte 2 of the Serializer KSV.
KSV3: Value of byte 3 of the Serializer KSV.
KSV4: Value of byte 4 of the Serializer KSV.
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