DS90UH926QSQE Datasheet, PDF (1/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
www.ti.com
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP
Check for Samples: DS90UH926Q
FEATURES
1
•2 Integrated HDCP Cipher Engine with On-Chip
Key Storage
• Bidirectional Control Interface Channel
Interface with I2C Compatible Serial Control
Bus
• Supports High Definition (720p) Digital Video
Format
• RGB888 + VS, HS, DE and Synchronized I2S
Audio Supported
• 5 to 85 MHz PCLK Supported
• Single 3.3V Operation with 1.8V or 3.3V
compatible LVCMOS I/O Interface
• AC-coupled STP Interconnect up to 10 Meters
• Parallel LVCMOS Video Outputs
• I2C Compatible Serial Control Bus for
Configuration
• DC-Balanced & Scrambled Data w/ Embedded
Clock
• Adaptive Cable Equalization
• Supports HDCP Repeater Application
• @ SPEED Link BIST Mode and LOCK Status
Pin
• Image Enhancement (White Balance and
Dithering) and Internal Pattern Generation
• EMI Minimization (SSCG and EPTO)
• Low Power Modes Minimize Power Dissipation
• Automotive Grade Product: AEC-Q100 Grade 2
qualified
• >8kV HBM and ISO 10605 ESD rating
• Backward Compatible Modes
DESCRIPTION
The DS90UH926Q deserializer, in conjunction with
the DS90UH925Q serializer, provides a solution for
secure distribution of content-protected digital video
within automotive entertainment systems. This
chipset translates a parallel RGB Video Interface into
a single pair high-speed serialized interface. The
digital video data is protected using the industry
standard HDCP copy protection scheme. The serial
bus scheme, FPD-Link III, supports full duplex of high
speed forward data transmission and low speed
backchannel communication over a single differential
link. Consolidation of video data and control over a
single differential pair reduces the interconnect size
and weight, while also eliminating skew issues and
simplifying system design.
The DS90UH926Q deserializer recovers the RGB
data, three video control signals and four
synchronized I2S audio signals. It extracts the clock
from a high speed serial stream. An output LOCK pin
provides the link status if the incoming data stream is
locked, without the use of a training sequence or
special SYNC patterns, as well as a reference clock.
The DS90UH926Q deserializer has a 31-bit parallel
LVCMOS output interface to accommodate the RGB,
video control, and audio data.
An adaptive equalizer optimizes the maximum cable
reach. EMI is minimized by output SSC generation
(SSCG) and Enhanced Progressive Turn-On (EPTO)
features.
The HDCP cipher engine is implemented in both the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
APPLICATIONS
• Automotive Display for Navigation
• Rear Seat Entertainment Systems
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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