DS90UH926QSQE Datasheet, PDF (48/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
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3.3V
DS90UH926Q
VDDIO
VDD33_A
C6
FB1
C4
VDD33_B
VDDIO
C7
C5
CAPP12
VDDIO
C8
C9
CAPR12
CAPI2S
C13
C10
Serial
FPD-Link III
Interface
C12 C11
C1
C2
C3
VDD33_B*
R₅
Host Control
C14
VDD33_B
VDD33_B
FB1 ± FB2: Impedance = 1 k: @ 100 MHz,
R₁
Low DC resistance (<1:)
C1 ± C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)
R₂
C4 ± C13 = 4.7 PF
C14 =>10 PF
R₁ and R₂ (see IDx Resistor Values Table 8)
R₃ and R₄ (see MODE_SEL Resistor Values Table 4)
R₅ = 10 k:
* or VDDIO = 3.3V+0.3V
VDD33_B
R₃
R₄
PASS
LOCK
CAPL12
R7
R6
R5
R4
R3
RIN+
R2
RIN-
R1
R0
CMF
G7
G6
G5
CMLOUTP
G4
G3
G2
CMLOUTN
G1
G0
OSS_SEL
OEN
B7
BISTEN
B6
BISTC / INTB_IN
B5
B4
PDB
B3
B2
B1
B0
SDA
SCL
HS
VS
DE
PCLK
ID[X]
I2S_CLK
I2S_WC
I2S_DA
MCLK
MODE_SEL
NC
RES ²
DAP (GND)
3.3V/1.8V
FB2
LVCMOS
Parallel
Video / Audio
Interface
Figure 23. Typical Connection Diagram
POWER UP REQUIREMENTS AND PDB PIN
The VDDs (V₃₃ and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating
voltage. When PDB pin is pulled to V_DDIO = 3.0V to 3.6V or V_DD33, it is recommended to use a 10 kΩ pull-up and
a >10 uF cap to GND to delay the PDB input signal.
All inputs must not be driven until V_DD33 and V_DDIO has reached its steady state value.
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