DS90UH926QSQE Datasheet, PDF (4/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS (continued)
Pin Name
BISTEN
BISTC
I2C
IDx
Pin #
44
16
56
SCL
3
SDA
2
Status
LOCK
32
PASS
42
FPD-Link III Serial Interface
RIN+
49
RIN-
50
CMLOUTP
52
CMLOUTN
53
CMF
51
Power⁽¹⁾ and Ground
VDD33_A,
VDD33_B
48, 29
V_DDIO
13, 24, 38
GND
DAP
Regulator Capacitor
CAPR12,
CAPP12,
CAPI2S
55, 57, 58
CAPL12
4
Others
NC
RES[1:0]
54
43.47
I/O, Type Description
I, LVCMOS BIST Enable Pin.
w/ pull-down 0: BIST Mode is disabled.
1: BIST Mode is enabled.
I, LVCMOS BIST Clock Select.
w/ pull-down Shared with INTB_IN
0: PCLK; 1: 33 MHz
I, Analog
I/O,
LVCMOS
Open Drain
I/O,
LVCMOS
Open Drain
I2C Serial Control Bus Device ID Address Select
External pull-up to V_DD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider.
See Figure 20
I2C Clock Input / Output Interface
Must have an external pull-up to V_DD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
I2C Data Input / Output Interface
Must have an external pull-up to V_DD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
O, LVCMOS
w/ pull down
LOCK Status Output Pin
0: PLL is unlocked, RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states are controlled
by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
O, LVCMOS
w/ pull down
PASS Output Pin
0: One or more errors were detected in the received payload
1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
I, LVDS
I, LVDS
O, LVDS
O, LVDS
Analog
True Input.
The interconnection should be AC Coupled to this pin with a 0.1 μF capacitor.
Inverting Input.
The interconnection should be AC Coupled to this pin with a 0.1 μF capacitor.
True CML Output
Monitor point for equalized differential signal
Inverting CML Output
Monitor point for equalized differential signal
Common Mode Filter. Connect 0.1 μF capacitor to GND
Power Power to on-chip regulator 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDD pin.
Power
Ground
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDDIO
pin.
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
CAP
CAP
Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAP pin.
Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
NC
GND
No connect. This pin may be left open or tied to any level.
Reserved. Tie to Ground.
(1) The VDD (V_DD33 and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
4
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UH926Q