DS90UH926QSQE Datasheet, PDF (17/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
www.ti.com
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
Table 1. SSCG Configuration
LFMODE = L (15 - 85 MHz)
SSCG Configuration (0x2C) LFMODE = L (15 - 85MHz)
SSC[2]
SSC[1]
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC[0]
L
H
L
H
L
H
L
H
Spread Spectrum Output
Fdev (%)
±0.9
±1.2
±1.9
±2.5
±0.7
±1.3
±2.0
±2.5
Fmod (kHz)
PCLK / 2168
PCLK / 1300
Table 2. SSCG Configuration
LFMODE = H (5 - <15 MHz)
SSCG Configuration (0x2C) LFMODE = H (5 - <15 MHz)
SSC[2]
SSC[1]
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC[0]
L
H
L
H
L
H
L
H
Spread Spectrum Output
Fdev (%)
±0.5
±1.3
±1.8
±2.5
±0.7
±1.2
±2.0
±2.5
Fmod (kHz)
PCLK / 628
PCLK / 388
Enhanced Progressive Turn-On (EPTO)
The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a
different time. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise.
In addition it spreads the noise spectrum out reducing overall EMI.
LVCMOS VDDIO Option
The deserializer parallel bus can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility.
The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
POWER DOWN (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the V_DDIO, where V_DDIO = 3.0V to 3.6V or V_DD33. To save power disable the link when the display
is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after V_DD33 and V_DDIO
have reached final levels; no external components are required. In the case of driven by the V_DDIO = 3.0V to 3.6V
or V_DD33 directly, a 10 kΩ resistor to the V_DDIO = 3.0V to 3.6V or V_DD33 , and a >10µF capacitor to the ground are
required (See Figure 23 Typical Connection Diagram).
STOP STREAM SLEEP
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer will
then lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the Serial Control Bus
Registers values are retained.
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