DS90UH926QSQE Datasheet, PDF (18/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
www.ti.com
SERIAL LINK FAULT DETECT
The serial link fault detection is able to detect any of following seven (7) conditions
1. cable open
2. “+” to “-“ short
3. “+” short to GND
4. “-“ short to GND
5. “+” short to battery
6. “-“ short to battery
7. Cable is linked incorrectly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control
Bus Register bit 0 of address 0x1C Table 9. The link errors can be monitored though Link Error Count of the
Serial Control Bus Register bit [4:0] of address 0x41 Table 9.
OSCILLATOR OUTPUT
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by
register Address 0x02, bit 5 (OSC Clock Enable). See Table 9.
PIXEL CLOCK EDGE SELECT (RFB)
The RFB determines the edge that the data is strobed on. If RFB is High (‘1’), output data is strobed on the
Rising edge of the PCLK. If RFB is Low (‘0’), data is strobed on the Falling edge of the PCLK. This allows for
inter-operability with downstream devices. The deserializer output does not need to use the same edge as the
Ser input. This feature may be controlled by register. See Table 9.
CLOCK-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) AND OUTPUT STATE
SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the DS90UH926Q completes its lock sequence to the input
serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is
available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and OSS_SEL
setting (Table 3) or register bit (Table 9). See Figure 8.
Inputs
Serial
input
X
X
X
Static
Static
Active
Active
PDB
0
1
1
1
1
1
1
OEN
X
0
0
1
1
1
1
Table 3. Output States
Outputs
OSS_SEL Lock
Pass
Data, GPIO, I2S
X
Z
Z
Z
0
L or H
L
L
1
L or H
Z
Z
0
L
L
L
1
L
0
H
1
H
Previous Status
L
Valid
L
L
Valid
CLK
Z
L
Z
L/OSC (Register bit
enable)
L
L
Valid
LOW FREQUENCY OPTIMIZATION (LFMODE)
The LFMODE is set via register (Table 9) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency of
the deserializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is
High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed,
a PDB reset is required.
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