DS90UH926QSQE Datasheet, PDF (30/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
3
ADD Register
(hex) Name
0x03 Configuration
[1]
Bit(s)
7
6
5
4
3
2
1
0
4 0x04 BCC
7:1
Watchdog
Control
0
5 0x05 I2C Control [1] 7
6:4
3:0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default Function
(hex)
0xF0
CRC
Generator
Enable
Filter
Enable
I2C Pass-
through
Auto ACK
RRFB
0xFE BCC
Watchdog
Timer
0x2E
BCC
Watchdog
Timer
Disable
I2C Pass
Through All
I2C SDA
Hold Time
I2C Filter
Depth
Descriptions
Reserved.
CRC Generator Enable (Back Channel)
1: Enable
0: Disable
Reserved
HS, VS, DE two clock filter When enabled, pulses less
than two full PCLK cycles on the DE, HS, and VS inputs
will be rejected
1: Filtering enable
0: Filtering disable
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
ACK Select
1: Auto ACK enable
0: Self ACK
Reserved
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
The watchdog timer allows termination of a control channel
transaction, if it fails to complete within a programmed
amount of time. This field sets the Bidirectional Control
Channel Watchdog Timeout value in units of 2
milliseconds.
This field should not be set to 0
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation"
I2C Pass-Through All Transactions
1: Enabled
0: Disabled
Internal I2C SDA Hold Time
It configures the amount of internal hold time provided for
the SDA input relative to the SCL input. Units are 50 ns.
I2C Glitch Filter Depth
It configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5 ns.
30
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