DS90UH926QSQE Datasheet, PDF (12/56 Pages) Texas Instruments – DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
AC TIMING DIAGRAMS AND TEST CIRCUITS
PCLK
V_DDIO
GND
RGB[n] (odd),
VS, HS
V_DDIO
GND
RGB[n] (even),
DE
Figure 2. Checker Board Data Pattern
V_DDIO
GND
CMLOUT
(Diff.)
EW
VOD (+)
EH
0V
EH
t_BIT (1 UI)
Figure 3. CML Output Driver
VOD (-)
t_CLH
80%
20%
t_CHL
Figure 4. LVCMOS Transition Times
V_DDIO
GND
RIN
(Diff.)
PCLK
(RFB = L)
RGB[7:0],
I2S[2:0],
HS, VS, DE
START
BIT
STOP
BIT
012
33
SYMBOL N
START
BIT
STOP
BIT
012
33
SYMBOL N+1
t_DD
SYMBOL N-2
SYMBOL N-1
Figure 5. Delay - Latency
SYMBOL N
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