TCM4400E Datasheet, PDF (8/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
voltage references
REFERENCE
VGAP Voltage on band gap (used for all other references)
Band gap output resistance
Band gap external decoupling capacitance
Band gap start time ( bit CHGUP=0 )
Band gap start time ( bit CHGUP=1)
VREF
Voltage reference of GMSK internal ADC and DAC : VVREF
Voltage reference output resistance
Voltage reference external decoupling capacitance
Voltage reference start time ( bit CHGUP=0 )
Voltage reference start time ( bit CHGUP=1)
VMID
Common-mode reference for baseband uplink: VVMID (Bit SELVMID=0)
Common-mode reference for baseband uplink: VVMID (Bit SELVMID=1)
Load resistance on Vmid output
MICBIAS Microphone-driving voltage (Bit MICBIAS=0)
Microphone-driving voltage(Bit MICBIAS=1)
Microphone-bias current drive capability (Bit MICBIAS= 1)
Microphone-bias current drive capability (Bit MICBIAS=0 )
ADCMID DC bias reference of the auxiliary ADCs
ADCMID external decoupling capacitance
IBIAS
Bias current adjust external resistance
MIN TYP
1.16 1.22
200
0.1
100
2.5
1.66 1.75
200
0.1
300
10
–10% Vdd/2
1.25 1.35
10
1.80 2.00
2.25 2.5
450 500
350 400
–10% Vdd/2
0.1
100
MAX
1.28
1.84
10%
1.45
2.20
2.75
10%
UNIT
Vdc
KΩ
µF
ms
ms
Vdc
KΩ
µF
ms
ms
Vdc
Vdc
KΩ
Vdc
Vdc
µA
µA
Vdc
µF
KΩ
master clock input (MCLK)
PARAMETER
Master clock signal frequency
Master clock duty cycle (Sinewave)
Maximum peak-to-peak amplitude
Minimum peak-to-peak amplitude
Common-mode input voltage
Input resistance at 13MHz (MCLK to ground)
Input capacitance at 13 MHz (MCLK to ground)
MIN
40%
0.5
VSS +0.5
4.1
12.5
NOM
13
MAX
60%
1.3
VDD –0.5
5
6.5
15
18
UNIT
MHz
Vpp
Vpp
Vdc
KΩ
pf
baseband uplink path
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I and Q D/A converters resolution
8
bit
Dynamic range on each output
Centered on VVMID
VVREF
Vpp
Differential output dynamic range with OUTLEV bit = 0† BULQP-BULQN or BULIP-BULIN
2 x VVREF
Vpp
Differential output dynamic range with OUTLEV bit = 1† BULQP-BULQN or BULIP-BULIN
8/15 x VVREF
Vpp
Output load resistance, differential
10
kΩ
Output load capacitance, differential
50
pF
Output common-mode voltage
Programmable by bit SELVMID
VVMID
V
I & Q output state in power down
Hi-Z
† _{Initial value after reset and at beginning of each burst are BULIP–BULIN=VREF and BULQP–BULQN=0 corresponding to a phase angle of 0°.}
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