TCM4400E Datasheet, PDF (45/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
Read operation from the downlink baseband codec is done using the TX part of the DSP/MCU serial interface
in the following 16-bit word format given in Table 5.
ÁÁÁÁD1ÁÁÁÁ59 ÁÁÁÁ1DÁÁÁÁ48 ÁÁÁÁD1ÁÁÁÁ37 ÁÁÁÁD1ÁÁÁÁ26 ÁÁÁÁD1ÁÁÁÁ15DAÁÁÁÁTAD1ÁÁÁÁ04 ÁÁÁÁTaD9ÁÁÁbÁ3leÁÁÁÁ5.D18ÁÁÁÁ26-BÁÁÁÁitDW7ÁÁÁ1ÁorÁÁÁÁd FD6ÁÁÁÁo0rmÁÁÁÁatA5ÁÁÁÁ4 ÁÁÁÁA4ÁÁÁ3ÁADÁÁÁÁDAR32ÁÁÁÁESSÁÁÁÁA21ÁÁÁÁÁÁÁÁA10ÁÁÁÁÁÁÁÁÁÁÁÁ00 ÁÁÁÁ
During reception of a burst, transfer of RF data from the downlink baseband codec is done using the transmit
part of the DSP serial interface in the following 16-bit word format: As the I and Q samples are coded with 16-bit
words, the data rate is 270833 × 16 × 2 which equals 8.66 Mbps. I & Q samples are differentiated by setting the
LSB to zero for I samples and to one for Q samples. Since the digital clock MCLK is 13 MHz, transfer is done
at 13 Mbps in burst mode. During burst reception the DSP serial interface is idled about 33% of the time.
ÁÁÁÁ_{D1ÁÁÁÁ155 ÁÁÁÁD1ÁÁÁÁ144 ÁÁÁÁD1ÁÁÁÁ133 ÁÁÁÁD1ÁÁÁÁ122 ÁÁÁÁD1ÁÁÁÁ111 ÁÁÁÁ}^T_D1^a_{1ÁÁÁÁ0}^b₀^le_{ÁÁÁÁ}^6._{D9ÁÁÁÁ}^F₉^or_{ÁÁÁÁ}^m_DD^a_{A8ÁÁÁT}Á₈^t_A^of_{ÁÁÁÁ}¹⁶_D7^-_{ÁÁÁ7}Á^Bit_{ÁÁÁÁ}^W_D6^o_{ÁÁÁ6}Á^rd_ÁÁÁ^TÁ^r_D^a_{55ÁÁÁ}ⁿÁ^sf_ÁÁÁ^eÁ^r_{D44ÁÁÁÁÁÁÁÁD33ÁÁÁÁÁÁÁÁD22ÁÁÁÁÁÁÁÁD11}ÁÁÁÁÁÁÁÁ_IÁÁÁÁ_D/0Q0 ÁÁÁÁ
DSP/MCU serial interface registers
The following internal register buffers are accessed using the DSP/MCU serial interface during manual
operation of the TCM4400E.
baseband uplink ramp delay register
Each bit position of the baseband uplink ramp-delay register is given in Table 7.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RESERVD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R = 0}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
Table 7. Uplink Ramp-Delay Register
BULRUDEL: BASEBAND UPLINK RAMP DELAY REG.
IBUFPTR DELD3 DELD2 DELD1 DELD0 DELU3 DELU2
R/W
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
DELU1
R/W
0
DELU0
R/W
0
ADDRESS: 1
R/W
0 0 0 0 1 1/0
<––– ACCESS TYPE
<–––VALUE AT RESET
DELU0 to DELU3 : Value of the delay of ramp-up start versus the rising edge of BENA
DELD0 to DELD3 : Value of the delay of ramp-down start versus the falling edge of BENA
IBUFPTR
: Writing a 1 in this bit initializes the pointer of the burst buffer to the base address.
(This is not a toggle bit and has to be set back to 0 to allow writing into the burst
buffer).
RESERVD
: Reserved bits for testing purposes
R/W
: A 1 indicates a read operation; a 0 indicates a write operation.
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