TCM4400E Datasheet, PDF (58/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
auxiliary functions control register 2 (see Table 33)
The values in the auxiliary function control register No. 2 set the operation parameters as described below:
APCSPD:
When cleared to 0, the APC clock is at 4 MHz; when set to 1, the APC clock is at 2 MHz.
IAPCPTR:
Setting to 1 initializes the pointer of the APC RAM to the base address. This is not a toggle
bit and has to be set to 0 to set APC RAM operational.
APCMODE: Select the equation used for APC waveform generation.
AGCW:
If cleared to 0, the automatic gain control path is powered down with the control of GSM
receive window (BDLON terminal) and AGCPD bit. If the AGCPD bit is set to 1, the
power down is controlled by AGCPD bit.
AGCPD:
This bit is functionally associated with AGCW bit. When this bit is set to 1, the automatic
gain control path is in power-down mode.
APCW:
If 0, the RF power control path is down powered with the control of GSM transmit window
(BULON) and with the control of APCPD bit. If the APCPD bit is set to 1, power down is only
controlled by APCPD bit.
APCPD:
This bit is functionally associated with the BBULW bit. When this bit is set to 1, the RF power
control path is in power-down mode.
Table 33. AUX Functions Control Register No. 2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _AGCW
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ R/W
0
AGCPD
R/W
0
AUXCTL2: AUXILIARY FUNCTIONS CONTROL REGISTER
APCW APCPD IAPCTR APCMODE RESERVD RESERVD
R/W R/W
R/W
R/W
R
R
0
0
0
0
0
0
APCSPD
R/W
0
RESERVD
R
0
ADDRESS: 20 R/W
1 0 1 0 0 1/0
<–ACCESS TYPE
<–VALUE AT RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{auxiliary A/D converter output register}
This register is read-only; however, if there is an attempt to write into it, an A/D conversion operation starts; see
Table 34. When the A/D conversion is finished, the AUXADC register is loaded and the A/D converter is
automatically down powered. During the conversion process the ADCEOC bit of the BSTATUS register is set.
This bit is reset automatically after AUXADC is loaded.
Table 34. AUX A/D Converter Output Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BIT9
R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
BIT8
R/W
0
AUXADC: AUXILIARY A/D CONVERTER OUTPUT REGISTER
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
BIT1
R/W
0
BIT0
R/W
0
ADDRESS: 21
R
1 0 1 0 1 1/0
<–ACCESS TYPE
<–VALUE AT RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{BIT 9 to 0:}
Output pf the 10-bit monitoring ADC.
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