TCM4400E Datasheet, PDF (38/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
radio window activation control
These internal blocks are powered up with the control of two bits. The first bit enables the window control of the
block activity; the second bit enables the power down.
First bit (PN):If cleared to 0, the function is powered down with the control of the corresponding GSM window
(BDLON/BULON terminal). If this first bit is set to 1, the power down is only controlled by the
second bit.
Second bit (PD): This bit is functionally associated with the first one. When this bit is loaded with 1, the function
is in power-down mode.
During transmit windows designated by the activity of the BULON terminal:
– Automatic power control (APC): bits APCW and APCPD of register AUXCTL2 are paired.
– Baseband uplink path: bits BBULW and BBULPD of register PWDNRG1 are paired.
– External reference voltage buffers VMID: bits VMIDW and VMIDPD are paired.
During receive windows designated by the activity of the BDLON terminal:
– Automatic gain control (AGC): bits AGCW and AGCPD of register AUXCTL2 are paired.
– Baseband downlink path: bits BBDLW and BBDLPD of register PWDNRG1 are paired.
external terminal PWRDN control
These internal blocks are powered under the control of two bits. The first bit enables the external terminal
PWRDN control of the block activity, the second bit enables the power down. Terminal PWRDN is active high.
First bit (PN):
If cleared to 0, the function is powered down with the control of PWRDN terminal. If this first
bit is set to 1, the power down is only controlled by the second bit (PD).
Second bit (PD): This bit is functionally associated with the first one. When this bit is set to 1, the function is
in power-down mode.
– For the digital serial interface to the DSP, bits BBSIPN and BBSIPD of register PWDNRG2 are paired.
– For the timing interface, bits TIMGPN and TIMGPD of register PWDNRG2 are paired.
– For the auxiliary A/D converters, bits ADCPN and ADCPD of register AUXCTL1 are paired.
– For the automatic frequency control (AFC) block, bits AFCPN and AFCPD of register AUXCTL1 are
paired.
– For the external reference voltage buffers MICBIAS, bits VREFPN and VREFPD of register PWDNRG2
are paired.
– For the internal reference band-gap buffers, bit VGAPPN determines whether the bandgap power down
is under control of the PWRDN bit.
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