TCM4400E Datasheet, PDF (19/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
MCU serial interface timing requirements (see Figure 3)
PARAMETER
tsu10
tv1
tv2
th9
th10
th11
tsu11
th12
tc
Setup time, UCLK stable before USEL↓
Hold time, UDX valid after USEL↓
Hold time, UDX valid after UCLK↑
Sequential transfer delay between 16-bit word acquisition tw pulse duration, USEL high
Hold time, UCLK↑ after USEL↓
Hold time, UCLK unknown after USEL↑
Setup time, data valid before UCLK↓
Hold time, data valid after UCLK↓
Cycle time, ULCK
MIN
20
3000
20
20
20
20
154
NOM
MAX
20
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
DSP serial interface timing requirements (see Figure 4)
PARAMETER
BCLKX BCLKX signal frequency ( Burst mode or Continuous mode depending on bit BCLKMODE)
BCLKX BCLKX duty cycle
tsu12
th12
tsu13
th13
BCLKR
Setup time, BFSX high before BCLKX ↓
Hold time, BFSX high after BCLKX ↓
Setup time, BDX valid before BCLKX ↓
Hold time, BDX valid after BCLKX ↓
BCLKR signal frequency
(Output BCLKDIR = 0)
(Input BCLKDIR = 1)
BCLKR BCLKR duty cycle
tsu14
th14
tsu16
th15
Setup time, BFSR high before BCLKR ↓
Hold time, BFSR high after BCLKR ↓
Setup time, BDR valid before BCLKR ↓
Setup time, BDR valid after BCLKR ↓
MIN
40%
20
20
20
20
40%
20
20
20
20
NOM
13
50%
4.33
50%
MAX
60%
13
60%
UNIT
MHz
ns
ns
ns
ns
MHz
ns
ns
ns
ns
voice timing requirements (see Figure 5)
PARAMETER
VCLK VCLK signal frequency ( Burst mode or Continuous mode depending on bit VCLKMODE)
VCLK VCLK duty cycle
tsu7
Setup time, VFS high before VCLK ↓
th6
Hold time, VFS high after VCLK ↓
tsu8
Setup time, VDX valid before VCLK ↓
th8
Hold time, VDX valid after VCLK ↓
tsu9
Setup time, VDR valid before VCLK ↓
th7
Hold time, VDR valid after VCLK ↓
MIN
40%
100
100
100
100
100
100
NOM
520
50%
MAX
60%
UNIT
kHz
ns
ns
ns
ns
ns
ns
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