TCM4400E Datasheet, PDF (47/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
baseband uplink I and Q offset registers
The baseband uplink I and Q offset registers contain the offset values for the I and Q components, respectively,
as shown in Tables 9 and 10.
Table 9. Uplink I Offset Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RESERVD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _R
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ULIOFF8
R/W
0
BULIOFF: BASEBAND UPLINK I OFFSET REGISTER
ULIOFF7 ULIOFF6 ULIOFF5 ULIOFF4 ULIOFF3 ULIOFF2
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
ULIOFF1
R/W
1
ULIOFF
R/W
1
ADDRESS: 3 R/W
0 0 0 1 1 1/0
<–ACCESS TYPE
<–VALUE AT RESET
ULIOFF0 to ULIOFF1 : Integration bits during calibration (to minimize sensitivity to noise)
ULIOFF2 to ULIOFF8 : Value of the offset on I channel
RESERVD
: Reserved bits for testing purposes
R/W
: A 1 indicates a read operation; a 0 indicates a write operation.
Table 10. Uplink Q Offset Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RESERVD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _R
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ULQOFF8
R/W
0
BULQOFF: BASEBAND UPLINK Q OFFSET REGISTER
ULQOFF7 ULQOFF6 ULQOFF5 ULQOFF4 ULQOFF3 ULQOFF2
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
ULQOFF1
R/W
1
ULQOFF0
R/W
1
ADDRESS: 4 R/W
0 0 1 0 0 1/0
<–ACCESS TYPE
<–VALUE AT RESET
ULQOFF0 to ULQOFF1 : Integration bits during calibration (to minimize sensitivity to noise)
ULQOFF2 to ULQOFF8 : Value of the offset on Q channel
RESERVD
: Reserved bits for testing purposes
R/W
: A 1 indicates a read operation; a 0 indicates a write operation.
baseband uplink I and Q D/A conversion registers
The I and Q component values generated by the I and Q uplink D/A converter during the conversion of analog
data are written to and read from the uplink I and Q D/A converter registers as shown in Tables 11 and 12.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RESERVD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _R
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
Table 11. Uplink I DAC Register
RESERVD
R
0
BULIDAC: BASEBAND UPLINK I DAC REGISTER
RESERVD RESERVD RESERVD RESERVD RESERVD RESERVD
R
R
R
R
R
R
0
0
0
0
0
0
RESERVD
R
0
RESERVD
R
0
ADDRESS: 6 R/W
0 0 1 1 0 1/0
<–ACCE0S TYPE
<–VALUE AT RESET
RESERVD
: Reserved bits for testing purposes
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