TCM4400E Datasheet, PDF (39/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
DSP voiceband serial interface
Voiceband serial digital interface consists of a bidirectional serial port. Both receive and transmit operations are
double buffered, thus allowing a continuous communication stream. The serial port is fully static and, thus,
functions with any arbitrary low-clocking frequency.
The transfer mode available on this port is:
Clock frequency
520 kHz
16-bit data packet
frame synchronization
VCLK is the output serial clock used to control the transmission or reception of the data, (see Figure 5). VCLK
can run in burst mode or continuous mode, depending on the VCLKMODE bit. The transmitted serial data (VDX)
is the serial data output; the frame synchronization (VFS) is used to initiate the transfer of transmit and receive
data. The received data (VDR) is the serial data input.
Each serial port includes four registers: the data transmit register (DXR), the data receive register (DRR), the
transmit shift register (XSR), and the receive shift register (RSR).
The voice serial interface has the same structure and timing diagram as the serial interface. One extra cycle
is generated before VFS, and two extra cycles are generated after the least significant bit (see Figure 5).
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