TCM4400E Datasheet, PDF (59/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
baseband status register
The baseband status register stores the baseband status as described in Table 35.
Table 35. Baseband Status Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RESERVD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R = 0}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ADCEOC
R
0
BSTATUS: BASEBAND STATUS REGISTER
RAMPTR BUFPTR
ULON
ULCAL
ULX
R
R
R
R
R
0
0
0
0
0
DLON
R
0
DLCAL
R
0
ADDRESS: 22 R
DLR 1 0 1 1 0
1
R
<–ACCESS TYPE
0
<–VALUE AT RESET
DLR:
This bit is set to 1 during conversion of a burst in the downlink path.
DLCAL:
This bit is set to 1 during offset calibration of the downlink path.
DLON:
When set to 1, it indicates that the downlink path is powered on.
ULX:
This bit is set to 1 during transmission of the burst in the uplink path.
ULCAL:
This bit is set to 1 during offset calibration of the uplink path.
ULON:
When set to 1, it indicates that the uplink path is powered on.
BUFPTR:
When set to 1, it indicates that the pointer of the burst buffer is at address zero.
RAMPTR:
When set to 1, it indicates that the pointer of the APC RAM is at address zero.
ADCEOC:
(ADC-end of conversion) when this bit is set to 1, an ADC conversion is in process.
Voiceband control register 4 (address 23)
Voiceband control register 4 (VBCTL4) is a read/write register (see Table 36) and contains the four programming
bits of VDLST as shown in Table 37.
Table 36. Voiceband Control Register 4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RESERVD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _R=0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
RESERVD
R=0
0
VBCTL4: VOICEBAND CONTROL REGISTER 4
RESERVD RESERVD RESERVD RESERVD VDLST3
R=0
R=0
R=0
R=0
R/W
0
0
0
0
0
VDLST2
R/W
0
VDLST1
R/W
0
VDLST0
R/W
0
ADDRESS: 23 R/W
1 0 1 1 1 1/0
<–ACCESS TYPE
<–VALUE AT RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Table 37. VDLST Status}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VDLST3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
VDLST2
0
1
1
1
0
1
0
0
1
0
1
VDLST1
0
0
0
1
1
1
1
0
0
0
0
VDLST0
0
1
0
0
0
1
1
0
0
1
1
SIDE TONE GAIN
Mute
–23 dB
–20 dB
–17 dB
–14 dB
–11 dB
–8 dB
–5 dB (nominal)
–2 dB
+1 dB
+1 dB
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