TCM4400E Datasheet, PDF (27/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
baseband uplink path (continued)
Timing Interface
Din
270 kHz
Burst
Register
Differential
Encoder
Burst Timing
Control
Gaussian
Filter
Integrator
–
Offset
+
Register
Cosine
Table
8-Bit
DAC
fs = 16 x 270 kHz
Low-Pass
Filter
BULIP
BULIN
I/Q Gain Unbalance
Power
Register
Ramp-Up
Shaper
To Power
Control DAC
Sine
Table
Offset
Register
8-Bit
DAC
Low-Pass
Filter
–
+
BULQP
BULQN
Figure 7. Functional Structure of the Baseband Uplink Path
baseband downlink path
The baseband downlink path includes two identical circuits for processing the baseband I and Q components
generated by the RF circuits. The first stage of the downlink path is a continuous-time second-order antialiasing
filter (see Figure 8) that prevents aliasing due to sampling in the A/D converter. This filter also serves as an
adaptation stage (input impedance and common-mode level) between external-world and on-chip circuitry.
TYPICAL FREQUENCY RESPONSE OF THE
ANTIALIASING FILTER
10
0
– 10
– 20
– 30
– 40
– 50
– 60
– 70
102
103
104
105
106
107
f – Frequency – Hz
Figure 8. Antialiasing Filter
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