TCM4400E Datasheet, PDF (31/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
RF power control
The RF power control section includes a register that is written to using the serial interfaces. An 8-bit D/A
converter processes the content of this register and determines the gain of the RF section power amplifier.
The reference of the 8-bit D/A converter (accessed by register AUXAPC) is provided by the ramp-up-shaper
D/A converter, which is a 5-bit D/A converter controlled by the APCRAM registers located in random access
memory (RAM). This area of RAM contains sixty-four 10-bit words. These are read from address 0 through
address 62 during the ramp-up sequence. They are read from 63 through 1 during the ramp-down sequence
at a rate of 4 MHz when bit APCSPD is at zero or at a rate of 2 MHz when bit APCSPD is at 1. The ramp-up
parameters are obtained from the five least significant bits of the RAM words. The ramp-down parameters are
obtained from the most significant bits of the RAM words. Content of address 0 must be identical with content
of address 1. Content of address 62 must be identical with content of address 63.
This RAM is loaded once, and its content determines the shape of the ramp-up and ramp-down control signal.
This means these control signals can be adapted to the response of the power amplifier used in the RF section.
The shape and timing of ramp-up and ramp-down waveforms are independent.
Timing of the ramp-up and ramp-down sequences is controlled internally; however, programming of the delay
register allows adjusting the power-control start time in a 4-bit range in 1/4-bit steps. The contents of the delay
register are referenced to the BENA signal, which determines the beginning of the burst-signal modulation. This
feature allows adjusting the timing of the control signal versus the I and Q components within 1/4-bit accuracy
as defined in the specification GSM 05.05.
When APC is in power-down mode or when APC level is zero, the analog output is driven to V_SS; see
Figure 12. During inactivity periods, the APC output is switched to V_SS to give low-current consumption to the
power amplifier (drain cutoff current of the RF amplifier);
BULON
BENA
Level 255
APC OUT
Level 1
Level 0
Offset = 120 mV
Figure 12. APC Output When APCMODE = 0
An offset of typically 120 mV ( 2 V swing) is added to the APC output to ensure level DAC linearity. Bit APCMODE
controls how this offset is added. When APCMODE is zero the APC output is given by
APCout = Shape value * ( Level value + Offset)
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