TCM4400E Datasheet, PDF (26/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
baseband uplink path (continued)
Timing for power up, offset calibration, data transmission, and power ramp-up is driven by control bits applied
to BULON (base uplink on), BCAL (calibration) and BENA (enable) (see Figure 1). The entire content of a burst,
including guard bits, tail bits, and data bits, is sent by the DSP using the DSP interface and then stored by the
TCM4400E in a burst buffer. Transmission start is indicated by the control bit BENA when the BULON is active.
The transmission, sequencing, and power ramp-up are then controlled by an on-chip burst timing control circuit
having a one-quarter-bit timing accuracy (see Figure 7). All data related to a burst to be transmitted, such as
bit data, ramp-up & ramp-down delay programmation, have to be loaded before the rising edge of BENA.
The burst length is determined by the time during which the BENA signal is active. Effective burst length is equal
to the duration of BENA + 32 one-quarter bits. The tail of the burst is controlled internally, which means that the
modulation is maintained for 32 one-quarter bits after BENA turns off to generate the ramp-down sequence and
complete modulation.
For each burst, the power control level can be controlled by using the serial interfaces to write the power level
value into the power register of the auxiliary RF power control circuitry. The power ramp-up and ramp-down
sequences are controlled by the burst sequencer, while the shape of the power control is generated internally
by dedicated circuitry, which drives the power control 5-bit and 8-bit D/A converters.
To minimize phase error, the I and Q channel dc offset can be minimized using offset calibration. Each channel
includes an offset register in which a value corresponding to the required dc offset is stored, controlling the dc
offset of the I channel and Q channel D/A converters. This value is set by a calibration sequence. Starting and
stopping the calibration sequence is controlled by the control bit BCAL using the timing interface when BULON
is active. During the calibration sequence, the digital value of I and Q is forced to zero so that only the offset
register value drives the D/A converters, and a low-offset comparator senses the dc level at the BULIP/BULIN
and BULQP/BULQN outputs and modifies the content of the offset registers to minimize the dc offset (see
Figure 7).
Gain unbalance can be introduced between I and Q channels to allow compensation of imperfections in RF
circuits. This gain unbalance is controlled through the mean of three program bits: IQSEL,G1, and G0 of
baseband uplink register BULCTL.
The power-down function is controlled with two bits. The first bit (BBULW of the PWDNRG1 register),
determines whether the baseband uplink path can be powered down with external GSM transmit window
activation (BULON). The second bit (BBULPD of the PWDNREG1 register) controls the activation of the
baseband uplink path. For more details about power-down control, see the power-down functional description
section.
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