TCM4400E Datasheet, PDF (24/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
voiceband serial interface timing considerations
Figure 5 shows the timing diagram for both transmit and receive voiceband serial interface operation.
The signal VCLK is the output serial clock used to control the transmission or reception of the data (see
Figure 5). The transmitted serial data (VDX) is the serial data output; the frame synchronization (VFS) is used
to initiate the transfer of transmit and receive data. The received data (VDR) is the serial data input.
Each serial port includes four registers that include the data transmit register (DXR), the data receive register
(DRR), the transmit shift register (XSR), and the receive shift register (RSR).
The voice serial interface has the same structure and timing diagram as the serial interface; one extra cycle is
generated before VFS, and two extra cycles are generated after the LSB.
XLOAD and RLOAD are internal signals.
VCLK
tsu7
tsu8
th6
th8
VFS
VDX
XLOAD
A15
A14
A13
A12
MSB
A3
A2
A1
A0
LSB
DXR
Loaded
VCLK
VFS
XSR
Loaded
tsu9
a. Audio-Serial-Port Transmit Operation
th7
VDR
RLOAD
A15
A14
A13
A12
MSB
A3
A2
A1
A0
LSB
b. Audio-Serial-Port Receive Operation
DDR
Loaded
Figure 5. Voiceband Serial Interface Timing Waveforms
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